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Pascal Andreas Meinerzhagen

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Publications associées (30)

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Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen

Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAMfor reasons such as high density, low bitcell leakage, logic compatibility, and suitability for 2-port memories. Themajor drawbacks of GC-eDRAMs are their limited data retention times ...

Institute of Electrical and Electronics Engineers2016

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In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

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Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by ...

Institute of Electrical and Electronics Engineers2016

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Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

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Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

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During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs ca ...

CRC Press2015

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The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated w ...

2015

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen, Georgios Karakonstantis

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

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Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power cons ...

Institute of Electrical and Electronics Engineers2014