Publications de Giovanni De Micheli

Area-Oriented Resubstitution For Networks of Look-Up Tables

Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino

This paper addresses the challenge of reducing the number of nodes in Look-Up Table (LUT) networks with two significant applications. First, Field-Programmable Gate Arrays (FPGAs) can be modelled as networks of LUTs, and minimizing the node count is impera ...

2025

The Council on Electronic Design Automation

Giovanni De Micheli

Institute of Electrical and Electronics Engineers (IEEE)2025

Area-Oriented Optimization After Standard-Cell Mapping

Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino

We address the problem of minimizing the area of circuits mapped to a technology library, with or without delay constraints. While traditional methods optimize first a technology-independent representation and then perform technology mapping to a library, ...

Association for Computing Machinery2025

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Giovanni De Micheli, Siang-Yun Lee

It is envisaged that spintronic logic devices will ultimately be utilized in hybrid CMOS-spintronic systems where signal interconversion between magnetic and electrical domains via transducers takes place. This underscores the vital role of transducers in ...

2025

Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron

Giovanni De Micheli, Alessandro Tempia Calvino

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Before physical design can be performed, AQFP technology mapping involves not only mapping logic into supported gate types but also legalizing the circuit to fulfil ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2025

Gradient Approximation of Approximate Multipliers for High-Accuracy Deep Neural Network Retraining

Giovanni De Micheli

Approximate multipliers (AppMults) are widely employed in deep neural network (DNN) accelerators to reduce the area, delay, and power consumption. However, the inaccuracies of AppMults degrade DNN accuracy, necessitating a retraining process to recover acc ...

Institute of Electrical and Electronics Engineers2025

SPFD-Based Delay Resynthesis

Giovanni De Micheli, Andrea Costamagna

We propose novel algorithms for post-mapping delay optimization, referred to as delay resynthesis. The state-of-the-art approach optimizes delay by rewriting with optimal local substructures. However, it is limited to local transformations, does not exploi ...

IEEE2025

Symmetry-Based Synthesis for Interpretable Boolean Evaluation

Giovanni De Micheli, Andrea Costamagna

Efficient evaluation of Boolean functions is a fundamental problem in computer science, impacting computational complexity and hardware performance. A natural way to evaluate Boolean functions is using circuits composed of two-input operators. However, syn ...

IEEE Computer Society2025

Lazy Man’s Resynthesis For Glitching-Aware Power Minimization

Giovanni De Micheli, Andrea Costamagna

This paper presents a novel resynthesis engine for minimizing the dynamic power of digital circuits. Traditional logic synthesis methods primarily focus on zero-delay toggles—logic state changes occurring between the start and end of a clock cycle. In cont ...

Institute of Electrical and Electronics Engineers2025

Scalable Sequential Logic Synthesis Using Observability Don’t Care Conditions

Giovanni De Micheli, Dewmini Sudara Marakkalage

Sequential logic synthesis expands the solution space compared to combinational logic synthesis by reasoning about the reachable states of memory elements, leading to better Power-Performance-Area (PPA) outcomes. As gate costs continue to rise in advanced ...

2025