Srinivasan Murali

Cette personne n’est plus à l’EPFL

Publications associées (45)

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A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Hamid Sarbazi-Azad, Dara Rahmati

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

2009

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

2009

Processor Speed Control with Thermal Constraints

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

2009

Synthesis of Networks on Chips for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

David Atienza Alonso, Luca Benini, Srinivasan Murali

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

IEEE Press2009

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

2009

Method to design network-on-chip (noc)-based communication systems

Giovanni De Micheli, Luca Benini, Srinivasan Murali

To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, ...

2008

Network-On-Chip Design and Synthesis Outlook

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

2008

Temperature Control of High Performance Multicore Platforms Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperature. Temperature gradi- ents and hot-spots not only affect the performance of ...

2008

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Giovanni De Micheli, David Atienza Alonso, Yusuf Leblebici, Srinivasan Murali, Stéphane Badel, Ilhan Hatirnaz

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

ACM Press New York, NY, US2007

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