Personne

Srinivasan Murali

Cette personne n’est plus à l’EPFL

Publications associées (60)

Method to design network-on-chip (noc)-based communication systems

Giovanni De Micheli, Luca Benini, Srinivasan Murali

To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, ...

2008

Temperature Control of High Performance Multicore Platforms Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperature. Temperature gradi- ents and hot-spots not only affect the performance of ...

2008

Network-On-Chip Design and Synthesis Outlook

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

2008

Designing Routing and Message-Dependent Deadlock Free Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

Springer2008

Timing-Error-Tolerant Network-on-Chip Design Methodology

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini

With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on ...

2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

An Application-Specific Design Methodology for On-chip Crossbar Generation

Giovanni De Micheli, Luca Benini, Srinivasan Murali

Designing a power-efficient interconnection architec- ture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effec- tively hand ...

Institute of Electrical and Electronics Engineers2007

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to ...

2007

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Bringing NoCs to 65nm

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

2007

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