Personne

Davide Sacchetto

Publications associées (52)

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A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

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Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ieee-Inst Electrical Electronics Engineers Inc2013

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This invention describes a novel electronic device consisting of one-or more-vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central se ...

2013

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Shashi Kanth Bobba, Michele De Marchi

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Giovanni De Micheli, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto, Michail Zervas, Shenqi Xie, Yusuf Leblebici

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

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We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

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In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching ...

Institute of Electrical and Electronics Engineers2012

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

Institute of Electrical and Electronics Engineers2012

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

Ieee-Inst Electrical Electronics Engineers Inc2012

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This paper proposes a new detection methodology based on memristive-effect registered on silicon nanowire. The nano-wires are fabricated by a lithographic technique that allows precise and selective etching at the nanoscale. The wires are obtained in three ...

Elsevier2012