Davide Sacchetto

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Publications associées (52)

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Alessandro Cevrero, Pierre-Emmanuel Julien Marc Gaillardon, Jury Sandrini, Tugba Demirci

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

2014

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Davide Sacchetto, Seniz Esra Küçük, Yusuf Leblebici, Clemens Benedict Nyffeler

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014

Memristive Biosensors Under Varying Humidity Conditions

Giovanni De Micheli, Sandro Carrara, Davide Sacchetto, Yusuf Leblebici, Camilla Baj-Rossi, Francesca Puppo, Akshat Dave

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The mem- ristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Ins ...

Institute of Electrical and Electronics Engineers2014

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Georg Fantner, Davide Sacchetto, Yusuf Leblebici, Oliver Peric, Zuhal Tasdemir

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures ...

2014

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Ambipolar silicon nanowire field effect transistor

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Michele De Marchi

This invention describes a novel electronic device consisting of one-or more-vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central se ...

2013

Applications of Multi-Terminal Memristive Devices: A Review

Giovanni De Micheli, Sandro Carrara, Davide Sacchetto, Michail Zervas, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Michele De Marchi, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

2013

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