Franz Xaver Pengg

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Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

Sammy Cerida Rengifo, Francesco Chicco, Christian Enz, Franz Xaver Pengg

This work presents the design of a 24-GHz digitally controlled oscillator (DCO) in an advanced 28-nm bulk CMOS technology for short-range frequency-modulated continuous-wave radar system-on-chip for mobile and Internet-of-Things devices. The power minimization is therefore the primary focus. The oscillator consumes a record low power of 1.2 mW at a 0.65-V supply voltage. It achieves a very large frequency tuning range (TR) of 5.8 GHz (27%) and a 150 kHz resolution without significantly degrading the phase noise (PN). The proposed design methodology results in a state-of-the-art -193 dBc/Hz FoM(T).

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

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A 2.4 GHz polar transmitter compliant with the IEEE 802.15.6 standard is presented in this paper. A Linearized class-C power amplifier, employing dynamic biasing is used to minimize the adjacent channel interference and satisfy the defined spectrum mask requirements. An FBAR based frequency synthesizer enables fast startup and channel switching times. It is capable of addressing all the channels within the MBAN and ISM bands (2.36-2.48 GHz). The transmitter was integrated in 65 nm CMOS technology. It provides 0 dBm of output power while drawing 8.7 mA of current from a 1.2 V supply. The standalone power amplifier exhibits peak efficiency of 16%. © 2015 IEEE.

IEEE2015

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A 2.4-GHz low power polar transmitter for wireless body area network applications

Christian Enz, Vladimir Kopta, Franz Xaver Pengg

A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the overdriven cascode class-C power amplifier used as the output stage, by dynamically adjusting the bias voltage of the cascode transistor. An equivalent baseband model of the transmitter is presented and used to optimize system parameters and give initial assessment of the achievable performance in terms of efficiency and linearity. Based on these simulations, parameters for transistor-level implementation of the bias circuit are derived. The transmitter is designed in a 65 nm CMOS technology. The post layout simulations indicate that the transmitter successfully meets the requirements of the IEEE 802.15.6 standard for wireless body area networks. The simulated amplifier consumes 4.75 mA from a 1.2 V supply while delivering 1.45 dBm of output power with a peak efficiency of 24 %. The entire transmitter, including the PLL, consumes 7.5 mA.

Springer Verlag2014

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