Substrate Current Modeling for high Temperature Smart Power BCD Technology

The electronics industry is present nowadays in the most various applications. A new type of technology for integrated circuits named BCD has started to be developed and appeared from the mid 1980’s. This new technology allows integrating bipolar transistors, high voltage MOS transistors named DMOS and standard CMOS technologies on one substrate. This new technology used in integrated circuits is called Smart Power (Power & Intelligence). Before that, power integrated circuits were developed only with bipolar technologies. These technologies are perfectly suitable for analogue functions such as audio amplification or charge commutation, but are not dedicated to the integration of logical functions. The motor control industry has demanded more and more solutions for smart management of motors. Those solutions are used for power window lifts where the circuit receives commands through LIN bus present in automobiles and is able to manage the motor autonomously. This type of applications requires more and more digital functions within the circuit. Without the integration of CMOS technologies, the targets of costs and performances can be achieved only using many integrated circuits. This induces issues of reliability, electromagnetic compatibility and space. This is why the family of circuits called Smart Power combining power components as well as logical functions is unavoidable in that field. The most important problem of Smart‐Power circuits is the perturbations induced by power components within the circuit itself. Those parasitic effects can affect and disturb highly the functionality of the integrated circuit and can even destroy the circuit or its main functionalities. Nowadays, it is very difficult, even hardly possible to predict the noise within the circuit substrate using the same modeling techniques as the ones used for transistor modeling. This work presents a new modeling strategy based on equivalent schematic interconnecting simple modeling elements. The particularity of the proposed elements is that the two types of charge carriers are taken into account when interconnecting these elements. The correct physical modeling of these charge transport phenomenon taking place in the substrate is then guaranteed. The advantages of this modeling technique for an integrated circuit designer are its simplicity to be implemented as well as a very short calculation time. The developed method has been used to model parasitic effects present in an industrial circuit. The results obtained are compared to current calculation method, as well as to measurements.