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Techniques for Fully Integrated Intra-/Inter-chip Optical Communication

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Techniques for Fully Integrated Intra-/Inter-chip Optical Communication

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Chattez avec Graph Search

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

3.5-D Integration: A Case Study

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Thermal Simulation of Liquid-Cooled Integrated Circuits

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Towards Multi-Fabric 3D Integration Architectures

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

Towards Multi-Fabric 3D Integration Architectures

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Thermal Simulation of Liquid-Cooled Integrated Circuits

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

3.5-D Integration: A Case Study