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Publication# Parallel architecture for high-speed analog-to-digital conversion

Résumé

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome these limits parallel architectures have been developed. The most commonly used it the one called "time-interleaved" conversion. This technique allows to achieve very-high sample-rates with circuits working at a lower frequency. The accuracy of "time-interleaved" systems is sensitive to sample-time errors. Some calibration techniques have been developed to reduce this sensitivity. They involve very sophisticated digital signal processing and, in most of the cases, they are not directly implemented on silicon but applied on measurement results in software. The goal of this thesis is to study the feasibility of a new parallel architecture for analog-to-digital conversion. This architecture must present a higher robustness to sample-time errors. The first part of this work is dedicated to time-interleaved converter. An analysis of their sensitivity to several imperfections, such as mismatches and systematic and random sample-time error is presented. This analysis is followed by a description of time-interleaved converter evolution, since the first implemented prototype to the current state of the art of the domain. The second part of this thesis focuses on the development of the new conversion technique called "frequency-interleaved". Two different approaches are studied: the first one is based on a Fourier series decomposition of the signal to convert and the second one is based on a Walsh series decomposition. During this study, theoretical and practical aspects are faced the one with the other, to combine signal processing and microelectronics together. It appears that the Fourier series approach offers modest performances and presents serious problems of implementation. Based on this study, the design of functional blocks of a Walsh series based system is proposed.

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Convertisseur analogique-numérique

vignette|Symbole normé du convertisseur analogique numérique
Un convertisseur analogique-numérique (CAN, parfois convertisseur A/N, ou en anglais ADC pour Analog to Digital Converter ou plus simpleme

Processeur de signal numérique

Un DSP (de l'anglais « Digital Signal Processor », qu'on pourrait traduire par « processeur de signal numérique » ou « traitement numérique de signal ») est un microprocesseur optimisé pour exécuter

Signal électrique

vignette|Signaux électriques sur l'écran d'un oscilloscope : signal rectanglaire (haut), signal harmonique ou sinusoïdal (bas).
Un signal électrique est une grandeur électrique dont la variation dans

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

Sampling has always been at the heart of signal processing providing a bridge between the analogue world and discrete representations of it, as our ability to process data in continuous space is quite limited. Furthermore, sampling plays a key part in understanding how to efficiently capture, store and process signals. Shannon's sampling theorem states that if the original signal is known to have a limited bandwidth, we can retrieve the signal from uniformly-spaced samples, provided that the sampling rate is greater than twice the highest frequency in the signal. Here, we see two key attributes: prior knowledge on the original signal (limited bandwidth) and a constrained sampling setup (uniform samples at a particular rate). In this thesis, we make weaker assumptions on the sampling setup by assuming that some information, such as the sample positions, is lost. We show that under proper prior knowledge, we can reconstruct the signal from its samples uniquely or up to some equivalence class. We start by the problem of linear sampling of discrete signals, where the sample values are known, but their order is lost. In general, the original signal is impossible to retrieve from the samples, but we show that by taking out symmetry from the sampling vectors, we can reconstruct the signal uniquely. We provide an efficient algorithm to find the sample orders and thus reconstruct the original signal. We also study the problem of reconstructing a continuous signal from samples taken at unknown locations. The lost sample locations take away any hope of uniquely retrieving the signal without prior knowledge. We show that this problem is equivalent to reconstructing a composite of functions from uniformly spaced samples. Then we provide an efficient algorithm that can recover bandlimited signals warped by a linear function uniquely given enough sampling frequency. We then investigate a problem, dubbed shape from bandwidth, where we have uniform samples from a picture (projection) of an unknown surface that is painted with an unknown texture. The goal is to reconstruct the shape of the surface from these samples. We show that having prior knowledge of the texture bandwidth provides us with enough information to reconstruct the surface from its picture. We provide reconstruction algorithms for both orthogonal and central projections and provide equivalence classes of solutions in each case. Next, in two consecutive chapters, using techniques from geometrical signal processing, we offer new designs for 3-D barcodes, whose information can be retrieved from a single projection using penetrating waves from an unknown direction. Because of the unknown scan direction, the correct correspondence of the samples to the information bits in the barcodes is lost. In this case, we use the known shape of the barcode as prior knowledge to estimate the unknown scan direction from the samples, and then transform the reconstruction as a linear problem that can be solved efficiently. Finally, we cover the theory of coordinate difference matrices (CDMs): matrices that store mutual differences between coordinates of points (sensors, microphones, molecules, etc.) in space. We show how we can leverage specific properties of these matrices, such as their low rank, as prior knowledge in order to reconstruct the position of the points in space using CDMs. We use our reconstruction algorithm to solve many real-life signal processing problems.

The transceivers of a wireless sensor network (WSN) have to fulfill the low-power and low-voltage constraints. The WiseNET project has already proven that it is possible to design a receiver working at 1V and consuming less than 2mW. However this transceiver is using OOK and wideband FSK modulations, which have a very poor spectral efficiency. A more complex modulation scheme is therefore needed, which requires an ADC in order to demodulate the signal in the digital domain. The ADC is then becoming the main bottleneck if the low-power consumption is targeted. This thesis aims at studying a next generation WiseNET transceiver using a more spectral efficient phase modulation scheme, particularly the new IEEE 802.15.4 standard, and it focuses on the design of a low-power and low-voltage ADC. The choice of the best receiver architecture depends on many factors, among which the power consumption, the integration suitability, the image rejection, the flicker and quantization noise, etc. Several architectures are analyzed in order to identify the trade-offs and select the most suitable for the IEEE 802.15.4 standard, i.e. a low-IF receiver with a quadrature band-pass ΔΣ modulator. From these considerations, a 2nd-order continuous-time quadrature band-pass ΔΣ modulator was implemented in a 0.18μm standard digital process. The design is focused on the constraints of low power consumption, low supply voltage and low complexity imposed by WSN. The availability of I and Q signals in the low-IF receiver enables a quadrature architecture, which allows to combine signal filtering, image rejection and quantization noise reduction. A continuous-time Gm-C implementation further combines the anti-alias function within the ADC and allows to achieve the 1V operation. The quadrature ΔΣ modulator is clocked at 72MHz and the center frequency is set to 3.75MHz with a bandwidth of 3MHz. The maximum measured signal-to-noise ratio is 36dB and the power consumption is only 450μW under 1V.