Convertisseur analogique-numérique

Résumé

vignette|Symbole normé du convertisseur analogique numérique Un convertisseur analogique-numérique (CAN, parfois convertisseur A/N, ou en anglais ADC pour Analog to Digital Converter ou plus simplement A/D) est un dispositif électronique dont la fonction est de traduire une grandeur analogique en une valeur numérique codée sur plusieurs bits. Le signal converti est généralement une tension électrique. Le résultat de la conversion s'obtient par la formule : Q = 2^n {V_e \over V_{ref}} où Q est le résultat de Conversion, Ve, la tension à convertir, n le nombre de bits du convertisseur et Vref la tension de référence de la mesure. Quantification Le processus de conversion repose sur la quantification d'un signal c'est-à-dire par son appariement au niveau quantifié le plus proche (que l'on pourrait rapprocher du phénomène de l'arrondi pour les nombres à virgule). La quantification d'un signal en dégrade sa richesse (il y a une perte d'information), c'est donc un

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https://fr.wikipedia.org/wiki/Convertisseur_analogique-num%C3%A9rique

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Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome these limits parallel architectures have been developed. The most commonly used it the one called "time-interleaved" conversion. This technique allows to achieve very-high sample-rates with circuits working at a lower frequency. The accuracy of "time-interleaved" systems is sensitive to sample-time errors. Some calibration techniques have been developed to reduce this sensitivity. They involve very sophisticated digital signal processing and, in most of the cases, they are not directly implemented on silicon but applied on measurement results in software. The goal of this thesis is to study the feasibility of a new parallel architecture for analog-to-digital conversion. This architecture must present a higher robustness to sample-time errors. The first part of this work is dedicated to time-interleaved converter. An analysis of their sensitivity to several imperfections, such as mismatches and systematic and random sample-time error is presented. This analysis is followed by a description of time-interleaved converter evolution, since the first implemented prototype to the current state of the art of the domain. The second part of this thesis focuses on the development of the new conversion technique called "frequency-interleaved". Two different approaches are studied: the first one is based on a Fourier series decomposition of the signal to convert and the second one is based on a Walsh series decomposition. During this study, theoretical and practical aspects are faced the one with the other, to combine signal processing and microelectronics together. It appears that the Fourier series approach offers modest performances and presents serious problems of implementation. Based on this study, the design of functional blocks of a Walsh series based system is proposed.

EPFL2009

Chargement

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel loss. Analog-to-digital converter (ADC) based links consisting of high-speed ADCs and digital signal processors enable the implementation of powerful equalization algorithms in the digital domain. Such systems are implemented using advanced technology nodes to benefit from the power and area advantages that the advanced technology nodes provide for the digital blocks. In addition to the speed, the power efficiency and the compatibility with technology scaling are important parameters in the design of ADCs used in such systems. Successive approximation register (SAR) ADCs have become a popular choice in wireline applications because of their power efficiency and compatibility with advanced technology nodes due to consisting of mostly digital blocks. This thesis focuses on high-speed SAR ADC design techniques to improve both conversion speed and power efficiency. First, a single-channel asynchronous SAR ADC design using a single comparator is presented to find out the achievable sampling rate with only one comparator. The 9-bit asynchronous SAR ADC prototype in 65 nm CMOS achieves 47.6 dB SNDR and 29.6 fJ/conv.-step figure-of-merit near Nyquist frequency at 222 MS/s and occupies an area of 0.017 mm2. Then, the use of comparator delay information for quantization is analyzed and a self-calibrated delay-based least significant bit extraction circuit, which achieves 3.35 dB SNDR for a 9-bit 200 MS/s with insignificant degradation in power consumption, speed, and area, is presented. Next, loop-unrolled (LU) SAR ADC topology, which uses multiple comparators to improve the SAR loop delay, and comparator offset calibration techniques in LU-SAR ADCs are reviewed. Common-mode voltage variation in LU-SAR ADCs due to comparator kickback and the common-mode dependency of the comparator offset are addressed. A common-mode adaptive background offset calibration for LU-SAR ADCs is proposed. The proposed calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between the comparators. Besides, the common-mode variation immunity of the proposed calibration scheme is exploited to optimize the figure-of-merit of the LU-SAR ADC. The prototype 8-bit LU-SAR ADC manufactured in 28 nm FDSOI achieves 42.57 dB SNDR and 22.8 fJ/conv.-step figure-of-merit at 800 MS/s with near Nyquist frequency input and occupies an area of only 0.0037 mm2. Lastly, an ADC-based receiver analog front-end (AFE) design in 28 nm FDSOI is presented and the feasibility of high order pulse amplitude modulation (PAM) is examined for a moderate-loss channel. The high order PAM compatible ADC-based AFE consists of a continuous-time linear equalizer and an 8 GS/s 8-way time-interleaved 7-bit SAR ADC with an embedded 2-tap feed-forward equalizer. All the equalization is implemented in the analog domain to avoid the circuit complexity and high power consumption of the digital equalization with high order modulation. The ADC-based AFE consumes 49.36 mW at 8 Gbaud, which corresponds to 1.54 pJ/bit at 32 Gb/s with PAM-16 and 2.06 pJ/bit at 24 GS/s with PAM-8.

EPFL2021

Chargement

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Chargement

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

EPFL2009

EPFL2007

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

EPFL2021