Publications associées à An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Shabnam Sheikhha

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks

Felix Schürmann, Michael Lee Hines, Bruno Ricardo Da Cunha Magalhães

State-of-the-art simulations of detailed neurons follow the Bulk Synchronous Parallel execution model. Execution is divided in equidistant communication intervals, with parallel neurons interpolation and collective communication guiding synchronization. Su ...

2020

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...

2019

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Marco Mattavelli, Simone Casale Brunet, Romuald Mosqueron, Endri Bezati

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

IEEE2019

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Apostolos Modas, Junaid Jameel Ahmad

This paper presents shared-variable synchronization approaches for dataflow programming. The mechanisms do not require any substantial model of computation (MoC) modification, and is portable across both for hardware (HW) and software (SW) low-level code s ...

IEEE2018

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given opt ...

2018

Spatial: A Language and Compiler for Application Accelerators

Christos Kozyrakis, Yunqi Zhang

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for pr ...

ASSOC COMPUTING MACHINERY2018

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

2017

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska, Junaid Jameel Ahmad

The exploration of different design configurations of dynamic dataflow programs executed on many-core or multi-core platforms is, in general, a very difficult task. Determining a close-to-optimal partitioning, scheduling and buffer dimensioning configurati ...

2017

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An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

Spatial: A Language and Compiler for Application Accelerators

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Chattez avec Graph Search

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Spatial: A Language and Compiler for Application Accelerators

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs