Publication

Improving Reliability of Embedded Systems through Dynamic Memory Manager Optimization using Grammatical Evolution

Publications associées (33)

À propos
Confidentialité
Mentions légales

Graph Chatbot

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Connectez-vous pour utiliser Chat avec Graph Search

Improving Reliability of Embedded Systems through Dynamic Memory Manager Optimization using Grammatical Evolution

Graph Chatbot

Chattez avec Graph Search

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

In-Memory Hardware and Architectural Extensions for Workloads Acceleration

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Gain-Cell Embedded DRAMs: Modeling and Design Space

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

In-Memory Hardware and Architectural Extensions for Workloads Acceleration

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Gain-Cell Embedded DRAMs: Modeling and Design Space