A Programmable Receiver for Communication Systems and Its Application to Impulse Radio

The design of a programmable receiver for an ultra wideband (UWB) communication is presented. The receiver is using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA) allowing a rapid performance evaluation for various system architectures and signal processing algorithms. To demonstrate the performance and the versatility of the receiver, a simple communication system and a localization system are implemented. The accuracy of the latter is presented for an indoor environment.

An Experimental Platform for an Indoor Location and Tracking System

Cyril Botteron, Frédéric Chastellain, Pierre-André Farine

In this paper, an experimental platform for indoor location and tracking using ultra wideband (UWB) impulse radio signals is presented and its performance measured. The platform has been developed entirely using standard electronic components that are commercially available. As principal goal, the experimental platform has been designed to allow a rapid performance evaluation for various system architectures and signal processing algorithms. Hence, the platform is as versatile as possible while remaining optimized for accurate location estimation. To meet these targets, the UWB receivers are implemented using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA). The ADC acquires directly the received radio frequency signal. The FPGA performs the required signal processing in real time and estimates the time of arrivals (TOAs) of the received pulses. The TOAs are transferred to a personal computer (PC), where the location of the transmitter is calculated. After the description of the hardware and the algorithms, the outcomes of a measurement campaign in a laboratory environment and the accuracy of the location system are presented.

2008

UWB-based Local Positioning System: from a small-scale Experimental Platform to a large-scale Deployable System

Cyril Botteron, Pierre-André Farine, Christian Robert, Phillip Tomé

A few years ago an experimental platform was designed and built in order to demonstrate the feasibility of Ultra-Wideband (UWB) technology applied to indoor positioning. This small-scale demonstrator proved to be a valuable research tool with the flexibility to study, test and assess the performance of various system architectures and signal processing algorithms. Based on this successful experience, the current follow-up R&D project aims to extend the research to other topics by pursuing two main objectives: a) designing and building a large-scale deployable UWB-based Local Positioning System (LPS), including its installation, calibration and operational testing in a real industrial environment; b) conceiving and developing Application Specific Integrated Circuits (ASICs) to target cost-competitive solutions. This paper addresses the main design issues analyzed during the requirements definition phase for this large-scale deployable LPS, considering that the new system should inherit whenever possible the design features already present in the small-scale experimental platform.

2010

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome these limits parallel architectures have been developed. The most commonly used it the one called "time-interleaved" conversion. This technique allows to achieve very-high sample-rates with circuits working at a lower frequency. The accuracy of "time-interleaved" systems is sensitive to sample-time errors. Some calibration techniques have been developed to reduce this sensitivity. They involve very sophisticated digital signal processing and, in most of the cases, they are not directly implemented on silicon but applied on measurement results in software. The goal of this thesis is to study the feasibility of a new parallel architecture for analog-to-digital conversion. This architecture must present a higher robustness to sample-time errors. The first part of this work is dedicated to time-interleaved converter. An analysis of their sensitivity to several imperfections, such as mismatches and systematic and random sample-time error is presented. This analysis is followed by a description of time-interleaved converter evolution, since the first implemented prototype to the current state of the art of the domain. The second part of this thesis focuses on the development of the new conversion technique called "frequency-interleaved". Two different approaches are studied: the first one is based on a Fourier series decomposition of the signal to convert and the second one is based on a Walsh series decomposition. During this study, theoretical and practical aspects are faced the one with the other, to combine signal processing and microelectronics together. It appears that the Fourier series approach offers modest performances and presents serious problems of implementation. Based on this study, the design of functional blocks of a Walsh series based system is proposed.

EPFL2009

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

EPFL2009