Publication

Integration of Engineered Source and Drain Extensions in Double Gate Mosfet with Sub-32nm Channel Length

Publications associées (73)

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Design Methodologies and CAD for Emerging Nanotechnologies

Shashi Kanth Bobba

With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main drive ...

EPFL2013

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Jean-Michel Sallese, Didier Bouvet, Farzan Jazaeri, Lucian Barbut

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

2013

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

2013

Defect states characterization of non-annealed and annealed ZrO2/InAlN/GaN structures by capacitance measurements

Nicolas Grandjean, Jean-François Carlin

InAlN/GaN metal-oxide-semiconductor structures with non-annealed and annealed ZrO2 gate insulators were characterized by capacitance-voltage (C-V) measurements. A significant capacitance hysteresis in both channel depletion and barrier accumulation regions ...

Amer Inst Physics2013

Bio/CMOS Interfaces and Co-Design

Sandro Carrara

Understanding and mastering the key area of CMOS biointerfaces requires a plurality of skills going beyond traditional disciplines. Indeed, biosensor design requires knowledge of biology and chemistry, surface and semiconductor technology, and electronics. ...

Springer2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

K-band single-chip electron spin resonance detector

Jens Anders

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single ...

2012

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011