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Barrier-layer scaling of InAlN/GaN HEMTs

Publications associées (32)

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CJM: A Compact Model for Double-Gate Junction FETs

Jean-Michel Sallese, Farzan Jazaeri, Matthias Bucher

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-n ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Jian Zhang

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Practical Applications of Tunnel Field Effect Transistors

Traditional metal-oxide-semiconductor field effect transistor scaling has advanced successfully over 50 years providing significant increases in transistor count per chip and operating frequency, thus enabled the built of ever more performant and complex s ...

EPFL2015

Leakage mechanisms and contact technologies in InAlN/GaN high electron mobility transistors

Lorenzo Lugani

GaN based electronic devices have progressed rapidly over the past decades and are nowadays starting to replace Si and classical III-V semiconductors in power electronics systems and high power RF amplifiers. AlGaN/GaN heterostructures have been, until rec ...

EPFL2015

GaN-on-insulator technology for high-temperature electronics beyond 400 degrees C

Nicolas Grandjean, Jean-François Carlin, Lorenzo Lugani

Lattice-matched InAlN/GaN high electron mobility transistors (HEMTs) have been prepared in a silicon-on-insulator (SOI)-like configuration. Here, this implies an ultrathin body 50 nm GaN channel/50 nm AlN nucleation layer material structure on sapphire wit ...

Iop Publishing Ltd2013

Tri-Gate Normally-Off GaN Power MISFET

Elison de Nazareth Matioli, Bin Lu

We present a new normally-off GaN transistor-the tri-gate normally-off GaN metal-insulator-semiconductor field-effect transistor (MISFET). Due to the excellent channel control of a new 3-D gate structure, a breakdown voltage of 565 V has been achieved at a ...

Ieee-Inst Electrical Electronics Engineers Inc2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Low Leakage Normally-off Tri-gate GaN MISFET

Elison de Nazareth Matioli, Bin Lu

A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-stat ...

Ieee2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012