Ferroelectric transistors with improved characteristics at high temperature

We report on the temperature dependence of ferroelectric metal-oxide-semiconductor (MOS) transistors and explain the observed improved characteristics based on the dielectric response of ferroelectric materials close to the Curie temperature. The hysteretic current-voltage static characteristics of a fully depleted silicon-on-insulator transistor, with 40 nm vinylidene fluoride trifluorethylene, and 10 nm SiO2 gate stack, are measured from 300 to 400 K. In contrast with conventional MOS field effect transistors (MOSFETs), the subthreshold swing and the transconductance show, respectively, a minimum and a maximum near the Curie temperature (355 K) of the ferroelectric material. A phenomenological model is proposed based on the Landau-Ginzburg theory. This work demonstrates that a MOSFET with a ferroelectric layer integrated in the gate stack could have nondegraded or even improved subthreshold swing and transconductance at high temperature even though the hysteresis window is reduced. As a consequence, we suggest that for ferroelectric transistors with appropriately designed Curie temperatures, the performance degradation of logic or analog circuits, nowadays operating near 100 degrees C, could be avoided. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3467471]

Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

Didier Bouvet, Mihai Adrian Ionescu, Livio Lattanzio, Giovanni Antonio Salvatore

The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FETs (Fe-FETs), when the temperature is increased. We explain our results by Landau's theory, which is also used to develop and validate an analytical model of ferroelectric capacitance. In order to validate the model, we fabricate and dc characterize a fully depleted silicon-on-insulator transistor with 10-nm SiO2 and 40 nm of vinylidene fluoride trifluorethylene P(VDF-TrFE) as a gate stack at different temperatures, ranging from 300 to 400 K. The transconductance and the subthreshold swing of a Fe-FET show a maximum and a minimum in correspondence to the Curie temperature of the ferroelectric, respectively. The proposed model and extraction is valid for any type of ferroelectric materials and Fe-FETs. Finally, this paper demonstrates that the performance degradation in a standard MOSFET (e. g., transconductance and subthreshold swing) at a high temperature of operation could be reduced or even suppressed in a Fe-FET if the Curie temperature of the gate stack is appropriately designed.

2011

Ferroelectric gate on AlGaN/GaN heterostructures

Lisa Malin

The capability of switching the spontaneous polarisation under an applied electric field in ferroelectric materials can be exploited for the use in low power, non-volatile, re-writable memory devices. Currently available commercially is ferroelectric random access memory, FeRAM, which allows for high speed, low voltage and greater write-erase endurance compared to its two main competitors, Flash and EEPROM, when using the one transistor – one capacitor configuration. However, it is desired to further optimise the configuration in order to obtain better densification, faster access time and better reliability. One way to do such is to pass from the ferroelectric capacitors and develop ferroelectric field effect transistors. Exploiting the phenomenon of ferroelectricity and integrating ferroelectrics with the semiconductor technology has not been simple. The FeFET has been demonstrated using a silicon-based transistor, however commercial devices are not available. Challenges arise mainly due to the high temperature deposition of perovskite ferroelectrics causing the degradation of the ferroelectric/semiconductor interface due to inter-diffusion. Acquiring long term retention of the transistor behavior has also been problematic due to phenomenons such as charge injection and depolarisation. In this thesis a new approach to the problem of semiconductor devices with a ferroelectric gate is explored. Instead of using a silicon-based device, semiconductor heterostructures are investigated. Combining the high mobility channel existing in semiconductor heterostructures, with the non-volatile switching of the polarisation in the ferroelectric gate can pave the way to novel future devices. The AlGaN/GaN semiconductor heterostructure was chosen for two main reasons. The first is a two dimensional electron gas, 2DEG, located at the AlGaN/GaN interface which possesses better transport properties than a single layered semiconductor. Secondly, GaN and its alloys are known to have large chemical and temperature stability making them ideal to withstand the high temperature deposition process of perovskite ferroelectrics. The deposition of two ferroelectric layers onto the AlGaN heterostructure were investigated. Lead zirconium titanate, PZT, a traditional perovskite ferroelectric deposited at high temperature, was chosen for its high remanent polarisation and low coercive field. An alternative ferroelectric gate, the co-polymer poly(vinylidene fluoride/trifluoroethylene), P(VDF/TrFE)(70:30) was deposited and of interest due its low crystallisation temperature and low dielectric constant. Its remanent polarisation is smaller and coercive field larger than that of PZT, but were determined sufficient to observe the depletion effect in the two dimensional electron gas. The goals accomplished in this research were: Development of Ferroelectric Gate Processing: Deposition processes of the ferroelectric layers were developed and optimised in order to obtain a high quality ferroelectric, while maintaining the original transport properties of AlGaNs 2DEG. The processing of HfO2 and MgO buffer layers were developed and investigated for their effects on limiting unwanted inter-diffusion and charge injection. PZT Gate on Al0.3Ga0.7N: The first successful development and observation of a PZT gate on a Al0.3Ga0.7N/GaN heterostrucutre was accomplished. A (111) oriented PZT(40:60) ferroelectric gate on the Al0.3Ga0.7N heterostructure depleted the sheet resistance of the 2DEG by a factor of three when poling the PZT layer with –40V directly to the conductive cantilever used in a piezoresponse force microscope. This decrease in sheet resistance was stable for more than three days. P(VDF/TrFE)(70:30) Gate on Al0.3Ga0.7N: The ferroelectric co-polymer P(VDF/TrFE) (70:30) was investigated as a gate on the Al0.3Ga0.7N heterostructure. When the P(VDF/TrFE) was poled with –30V to a top electrode the sheet resistance was modulated by a factor three, however there was no retention of this modulation. Ferroelectric Spontaneous Polarisation on a Semiconductor Heterostructure: It was theoretically derived that when depositing a ferroelectric layer onto a semiconductor heterostructure its spontaneous polarisation is dramatically reduced due to the depolarisation field and may be suppressed completely. This decay in spontaneous polarisation can be minimised by using a ferroelectric layer with a small dielectric constant, which justifies the use of ferroelectric polymers as the gate material. Domain Writing:The technique of domain writing using piezoresponse force microscopy showed that it was possible to create domain patterning on the ferroelectric layers that were deposited onto the Al0.3Ga0.7N heterostructure with sub-micron line resolution, on the order of 300nm or better. Using ferroelectrics on semiconductors is not only limited to ferroelectric memory devices. Other applications could be ferroelectric nano-lithography, where a ferroelectric pattern is written with a piezoresponse force microscope, PFM, and this pattern is projected onto the transistors channel, potentially creating quantum/ballistic devices. The challenge of integrating ferroelectrics with semiconductors has yet to be fully understood. One of the main advancements that was reached with this research is the understanding of the decrease of the spontaneous polarisation when a ferrroelectric layer is deposited onto a semiconductor heterostructure of finite thickness. The maximisation of the ferroelectrics polarisation on 20nm of Al0.3Ga0.7N can be obtained when minimising the dielectric constant of the ferroelectric layer. The current challenge is to get a better physical understanding of the limitation of the retention of the spontaneous polarisation, while discovering methods for its improvement.

EPFL2007

The Curie temperature as a key design parameter of ferroelectric Field Effect Transistors

Didier Bouvet, Mihai Adrian Ionescu, Livio Lattanzio, Giovanni Antonio Salvatore

Interest in Ferroelectric FETs originates from their potential as non-volatile memories and, more recently, as abrupt switches. In this work, we focus on the role of the Curie temperature of the gate stack on the performance of Fe-FETs. The proposed study is based on thin film SOI Fe-FETs using organic ferroelectric gate stacks (45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO2). The device static characteristics are investigated from 25°C up to 155°C, from ferroelectric to paraelectric phase. We report a maximum of the transconductance at the Curie Temperature (Tc), where the ferroelectric material loses its spontaneous polarization and the transistor loses its hysteresis. The reported increase of current and transconductance with the temperature up to Tc are in contrast with the behavior in any conventional MOSFET. The experimental results are supported by an appropriate analytical model. We suggest that the Curie Temperature of the gate stack is a key design parameter for the use of Fe-FETs as non-hysteretic switches with increased on-current, close or beyond Tc, or as memory cells, in the hysteretic domain, much below Tc.

IEEE2010

Ferroelectric gate on AlGaN/GaN heterostructures

Lisa Malin

EPFL2007