Nanoscale strain characterisation for ultimate CMOS and beyond

Strain engineering is used to maintain Moore's Law in scaled CMOS devices and as a technology booster for More-than-Moore devices in the nanoelectronics era. Strain is crucial because of its ability to increase electron and hole mobilities in Si. However, accurate correlations between electrical performance and strain measurements are needed to enable the necessary feedback between materials, processing and devices to achieve best possible solutions. In this work, we outline new methods for sensitive 3D profiling of strain on a nanoscale. High-resolution vertical and lateral strain profiles applicable to both global (biaxial) and process-induced (uniaxial) strained Si devices are demonstrated. Raman spectroscopy is pushed to its present limit for precise analysis of strain in small geometry devices, including the use of tip-enhanced Raman spectroscopy (TERS) to improve the spatial resolution further. TERS maps are compared with atomic force microscopy data collected simultaneously and show that variations in surface morphology correlate directly with strain in the epitaxial layers. Sub-nm strain profiling is applied to strained Si and SiGe MOSFET channels. Strain is profiled across patterned uniaxial strained-Si-on-insulator structures and analysed in bended nanowire transistors. Finally strain is investigated across the channel regions of electrically measured SiGe p-MOSFETs. Good agreement between nanoscale strain measurements and finite element modelling is demonstrated. Sample preparation is included in the analysis and genuine effects of processing are investigated. (C) 2009 Elsevier Ltd. All rights reserved.