A power-efficient, current-mode, binary-tree min / max circuit for Kohonen self-organizing feature maps and nonlinear filters

A novel current-mode, binary-tree Min / Max circuit for application in analog neural networks and filters has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that determine Min or Max signal. The circuit realized in the CMOS 0.18 μm process offers a precision of 99.5% at data rate of 2.5 MS/s and energy of 0.5 pJ per input.

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Rafal Tomasz Dlugosz
2010
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https://infoscience.epfl.ch/record/162196?ln=fr

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Concepts associés (12)

Concepts associés

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Publications associées (15)

Publications associées

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Circuit intégré

Le circuit intégré (CI), aussi appelé puce électronique, est un composant électronique, basé sur un semi-conducteur, reproduisant une ou plusieurs fonctions électroniques plus ou moins complexes, in

Neural network

A neural network can refer to a neural circuit of biological neurons (sometimes also called a biological neural network), a network of artificial neurons or nodes in the case of an artificial neur

Réseau de neurones artificiels

Un réseau de neurones artificiels, ou réseau neuronal artificiel, est un système dont la conception est à l'origine schématiquement inspirée du fonctionnement des neurones biologique

Low power current-mode binary-tree asynchronous Min/Max circuit

Rafal Tomasz Dlugosz

A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20 μA and data rate of 11 MHz the circuit dissipates 505 μW, while for the signals of 200 nA and data rate of 500 kHz the power dissipation is reduced to 1 μW. The prototype circuit with four inputs, realized in the CMOS 0.18 μm technology, occupies the area of 1800 μm2.

2010

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A Low Power Current-Mode Binary-Tree WTA / LTA Circuit for Kohonen Neural Networks

Rafal Tomasz Dlugosz

A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that allows to determine either the Min or the Max signal, depending on the configuration. The circuit realized in the TSMC CMOS 0.18 μm process offers a precision of about 99 % at the data rate of 3.5 MSps and energy consumption of about 0.7 pJ per one input signal per cycle.

Technical University of Lodz, Department of Microelectronics & Computer Science2009

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Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Rafal Tomasz Dlugosz

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-mu m technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 mu m(2). When operating in the L2 mode, the circuit dissipates 85 mu W of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 mu W from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

Institute of Electrical and Electronics Engineers2016

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