Microcamera Embedded in a Wristwatch

The presentation reports upon the conception and realization of a miniature very low-power microcamera system that has been embedded in a wristwatch so as to enable the spontaneous capture of photographs in everyday life based on timekeeping devices the users would naturally wear. The designed microcamera system is fully operational and incorporates specific optics and a color VGA format based image sensor, a viewfinder enabling the selection of the scene to be captured, an image preprocessing step for color interpolation and white/color balance, followed by a dedicated JPEG compatible still image compression algorithm producing fixed-sized encoded images. Finally, the user is given the possibility to screen a posteriori (postview mode) the set of images captured, e.g. to erase less interesting ones in order to liberate the corresponding storage space. The user interface is composed of a particular display usually indicating the time, that is switching into a camera management mode for the acquisition and postview of photographs. Moreover, the camera can communicate with a personal computer through a cradle either to download the set of photographs acquired, or to upload a set of operational parameters, while simultaneously reloading the accumulator supplying the microcamera of the wristwatch. The technological challenge induced by the dense integration requirement of the numerous peripheral devices, including the central processing capabilities, the user and communication interfaces, and the tight power consumption constraints to be fulfilled, ask for the elaboration of numerous innovative solutions out of which only few were published so far. The purpose of the presentation is to provide insight into the system organization and its breakdown into original inter-playing hardware and software components, which were finally validated by the realization of an industrial prototype and demonstrator. The multi-fold experience collected by the partners in the design proce- ss is of course nurturing further activities, and, from a didactic viewpoint, offered the opportunity to set up practical laboratories that were dispensed in the realm of the Summer Schools Highlights in Microtechnology coordinated by the European Associated Laboratory (LEA) and more recently funded by the EU FP6 Marie Curie programme.

Adding limited reconfigurability to superscalar processors

Marc Epalza

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane control assistance, almost all electrical household appliances, and the almost ubiquitous Personal Computer. Application-Specific Integrated Circuits (ASICs) were traditionally used for their high performance and low manufacturing cost, and were designed specifically for a single application with large volumes. But as lower product lifetimes and the pressures of fast marketing increased, ASICs' high design cost pushed for their replacement by Microprocessors. These processors, capable of implementing any functionality through a change in software, are thus often called General Purpose Processors. General purpose processors are used for everyday computing tasks, and found in all personal computers. They are also often used as building blocks for scientific supercomputers. Superscalar processors such as these require ever more processing power to run complex simulations, video games or versatile telecoms services. In the case of embedded applications, e.g. for portable devices, both performance and power consumption must be taken into account. In a bid to adapt a processor to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only for some specific applications with large parallelism, after a detailed study of the algorithm. Even though this process can be automated, it still requires large computing resources, and cannot be performed at run time. To reduce the loss in speed compared to custom logic, it is possible to limit the reconfigurability to increase the breadth of applications where performance can be improved. However, as the application space increases, a careful analysis and design of the reconfigurability is required to minimize the speed loss, notably when dynamic reconfiguration is considered. As a case study, we analyze the feasibility of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be executed by the FPU, this idle hardware only increases power consumption without enhancing performance. This is often the case in non-scientific applications and even many recent and detailed video games which make heavy use of hardware display accelerators for 3D graphics. In a fast multiplier such as can be found in the FPU of a high performance processor, the logic to perform multiplication is a large tree of compressors to add all the partial products together. It is possible to add logic to allow the reconfiguration of part of this tree as several extra Arithmetic and Logic Units (ALU). This requires a detailed timing analysis for both the reconfigurable FPU and the extra ALUs, taking into account effects such as added wires and longer critical paths. Finally, the algorithm to decide when and how to reconfigure must be studied, in terms of eciency and complexity. The results of adding this limited reconfigurability to a mainstream superscalar processor over a large set of compute intensive benchmarks show gains of up to 56% in the best case, with an average gain of 11%. The application to an idealized huge top processor still shows slightly positive average gains, as the limits of available parallelism are reached, bounded by both the application and many of the characteristics of the processor. In all cases, binary compatibility is maintained, allowing the re-use of all existing software. We show that adding limited reconfigurability to a general purpose superscalar processor can produce interesting gains over a wide range of applications while maintaining binary compatibility, and without large modifications to the original design. Limited reconfigurability is worthwhile as it increases the design space, allowing gains to apply to a larger set of applications. These gains are achieved through careful study and optimization of the reconfigurable logic and the decision algorithm.

EPFL2004

Dispositif de reperage d'un homme ou d'un objet dans un milieu liquide

Michel Declercq, Patrick Favre

The invention concerns a device for automatically and rapidly locating (10) a person or an object at sea in poor meteorological conditions, comprising a radio wave transmitting device (20) provided on the person or the object and a reception device (30), provided in a boat, and designed to receive directly said waves and to process them without any other intermediary than the radio link (40) established between them. The transmitting device (20) comprises a transmitter (21) supplied by a power source (23), and delivering a radio signal to an antenna (22). Said transmitter is activated by an actuating member (24). The reception device (30) consists of a receiver (31) for the signal transmitted by the transmitter (21) and picked up by an antenna array (32) co-operating with an antenna switch (33). The antenna array (33) is connected to the receiver (31) whereof an output is connected to said unit processing (34) the received signal. A display unit (37), connected to said processing unit (34) via a user interface (35), enables the display of the information delivered by said unit (34). An audio warning (36) is connected to the activation of the transmission device (20).

2004

Adding limited reconfigurability to superscalar processors

Marc Epalza

EPFL2004