Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier

A conception as well as a CMOS implementation of the analog, ultra low power and fully parallel image processor have been presented in this paper. Proposed circuit bases on the 2-D FIR filters realized using the Gilbert vector multiplier. Proposed filter enables realization of various lowpass and highpass 2-D FIR filter masks. Both the mask dimensions and values of the filter coefficients can be programmed using several dozen digital signals and several DC currents. Proposed image processor does not use the clock generator, what simplifies the overall circuit's structure and reduces the noise level. An example (6times6) image processor that enables filtering with a 3times3 mask has been implemented in CMOS 0.18 mum process. This circuit calculates 36 pixels in parallel every 1 mus, dissipating power about 20 muW. The image resolution can be easily enlarged by a parallel connection of many designed 6times6 cells.

Asynchronous front-end asic for x-ray medical imaging applications implemented in CMOS 0.18μm technology

Rafal Tomasz Dlugosz

An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modular structure enables an easy realization of larger systems with even hundreds of channels. Various new circuit solutions have been proposed by author and used in the circuit, such as: an asynchronous output multiplexer, a pulse shaper and a peak detector with a built-in clock generator, which activates the circuit only in the situation when a new impulse occurs at the input. This technique allows for very low power dissipation. In the worst case scenario, i.e. when all channels would be active at the same time, the power dissipation is kept below 2 mW. By introducing an efficient RESET mechanism that turns off a given channel just after reading out the information, the counting rate of a single channel has been increased to about 3 MSps. The proposed circuit solutions allow for a very low chip area usage that for a single channel is equal to 0.021 mm2, while the total chip area is equal to 0.17 mm2.

2008

Analysis and optimization of passive UHF RFID systems

Jari-Pascal Curty

Radio Frequency IDentification (RFID) is an automatic identification method, relying on storing and remotely retrieving data using devices called RFID tags or transponders. An RFID tag is a small object that can be attached to or incorporated into a product, animal or person. RFID tag contains antenna to enable it to receive and respond to Radio-Frequency (RF) queries from an RFID reader or interrogator. Passive tags require no internal power source, whereas active tags require a power source. As of today (2005), the ubiquitous computing and ambient intelligence ideas are making their way. In order for these to become a reality, a number of key technologies are required. Briefly, these technologies need to be sensitive, responsive, interconnected, contextualised, transparent and intelligent. RFID is such a technology and more particularly passive RFID tags. But, in order to deliver the necessary characteristics that could trigger ambient intelligence, there are some challenges that need to be addressed. Remote powering of the tags is probably the most important. Issues concerning the antenna-tag interface, as well as the rectifier design, that allows the RF signal to be converted to Direct Current (DC) are in pole position. Secondly, the communication link and the reader should be optimized. The RF signal that contains the tag data suffers from a power of four decay with the distance between tag and reader. As a result, both the reader sensitivity and the tag backscattered power efficiency have to be maximized. Long-range powering, as well as sufficient communication quality, are the guidelines of this work. This research project proposes a linear two-port model for an N-stage modified-Greinacher full wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameters values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. Also presented in this work is an experimental procedure to measure how the impedance modulation at the tag side affects the signal at the reader. The method allows the tag designer to efficiently predict the effect of modulator design at system level and gives an useful instrument to choose the most appropriate impedances. Finally, the design of a fully integrated remotely powered and addressable RFID tag working at 2.45 GHz is described. The achieved operating range at 4 W Effective Isotropically Radiated Power (EIRP) reader transmit power is 12 m. The Integrated Circuit (IC) is implemented in a 0.5 μm silicon-on-sapphire technology. A state of the art rectifier design achieving 37% of global efficiency is embedded to supply energy to the transponder. Inductive matching and a folded-dipole antenna are key elements to achieve these performances. The necessary input power to operate the transponder is about 2.7 μW.

EPFL2006

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.