Current Mode Euclidean Distance Calculation Circuit for Kohonen's Neural Network Implemented in CMOS 0.18μm Technology

Rafal Tomasz Dlugosz
2007
Article de conférence

In this paper we present analog current mode Euclidean distance calculation (EDC) block, which calculates the distance between two current vectors. The proposed circuit is an important part of the CMOS-implemented Kohonen’s neural network (KNN) designed for medical applications. The input data vector is compared with the weights’ vector in each neuron in proposed KNN. The neuron, whose weights are the closest to the input training vector becomes the winner and in the next step changes its weights. Proposed EDC block performs several operations such as: subtraction, squaring and summing of the current signals. The output current is the exact measure of the Euclidean distance. Proposed circuit dissipates power 15 μW from 1.5 V voltage supply, working with 20 MHz input data frequency. The signal frequency as well as the power dissipation may be scaled down to 1 MHz and 300 nA. Proposed EDC circuit, in CMOS 0.18 μm technology, occupies area about 500 μm2.

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Rafal Tomasz Dlugosz
2007
Article de conférence

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https://infoscience.epfl.ch/record/167718?ln=fr

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Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Rafal Tomasz Dlugosz

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-mu m technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 mu m(2). When operating in the L2 mode, the circuit dissipates 85 mu W of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 mu W from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

Institute of Electrical and Electronics Engineers2016

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Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

Rafal Tomasz Dlugosz

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18 mu m technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.

Institute of Electrical and Electronics Engineers2011

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Low power current-mode binary-tree asynchronous Min/Max circuit

Rafal Tomasz Dlugosz

A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20 μA and data rate of 11 MHz the circuit dissipates 505 μW, while for the signals of 200 nA and data rate of 500 kHz the power dissipation is reduced to 1 μW. The prototype circuit with four inputs, realized in the CMOS 0.18 μm technology, occupies the area of 1800 μm2.

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