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An integrated chip for DNA hybridization detection was realized in a standard CMOS process: it hosts 80 biosensors subdivided in 2 channels, as well as D/A and A/D converters for electrical stimulation and readout. A microfluidic system, bonded on the surf ...
Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...
A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each ...
Institute of Electrical and Electronics Engineers2014
The paper presents a new initialization mechanism based on a Convex Combination Method (CCM) for Kohonen self-organizing Neural Networks (NNs) realized in the CMOS technology. A proper selection of initial values of the neuron weights exhibits a strong imp ...
We present a fully integrated detector suitable for active tracking of interventional devices in MR-guided interventions. The single-chip microsystem consists of a detection coil, a tuning capacitor, an intermediate frequency downconversion receiver, and a ...
Techniques based on spin resonance effects are amongst the most powerful analytical methods in both modern chemistry and medicine. Recent years have seen a trend toward scaled-down detection coils, exploiting the fact that a reduction of the detector size ...
The advent of single-photon detectors known as Single-Photon Avalanche Diodes in standard CMOS technology opened the way to new perspectives in integrating these ultra sensitive light sensors with digital logic. Light has some interesting properties that a ...
We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...
Institute of Electrical and Electronics Engineers2011
This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the req ...
Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...