Single-Photon Techniques for Standard CMOS Digital ICs

The advent of single-photon detectors known as Single-Photon Avalanche Diodes in standard CMOS technology opened the way to new perspectives in integrating these ultra sensitive light sensors with digital logic. Light has some interesting properties that attracted researchers in computer and electronics for a long time. Its weightlessness nature makes it a candidate to replace electrons when it didn't already do so. This is particularly true for long distance data transfers. However a new trend can be observed. Researchers are looking into photonics, the science of light, for short distance communications as well. Power efficiency is one of the reasons of this trend. In fact, photons, the elementary particles of light, don't suffer of resistive, capacitive, or inductive effects like electrons do. The wavelike nature of light can also free designers from problems such as cross-talk and side-channel noise injection while taking advantage of interference. However photonics is still not the panacea and we don't believe it will ever completely replace electronics. Most certainly a combination of the two will be adopted to take advantage of both worlds. CMOS digital Integrated Circuit (IC) design faces many challenges and it is not clear whether technology will still provide small footprints, high performance, and low power in the future. Photonics with SPADs can answer some of these questions. In this work, we present three investigations where SPAD photonics is integrated within digital CMOS technology. The main contributions of this thesis are threefold: single-photon CMOS communication paradigms, single-photon processing and readout techniques, single-photon clocking and synchronization methods. Single-photon communication was achieved using a combination of SPADs and ultra-fast TDCs in a pulse position modulation scheme. In this context, theoretical channel capacity limits in the presence of noise and other non-idealities typical of SPADs were derived; a TDC with a resolution of 17 ps was demonstrated in a standard FPGA fabric. To the best of our knowledge, at the time of this writing, this is the highest reported resolution for a TDC of this kind. Single-photon processing and readout was achieved in several technologies, focusing on image sensor design, whereby massive parallel architectures were studied and implemented in CMOS. Single-photon clocking and synchronization was demonstrated allowing potentially zero skew systems irrespective of the chip area. The power benefits of this approach in embedded systems with instruction set extensions are particularly interesting. The thesis makes use of SPAD technology implemented in CMOS for a number of applications creating a bridge between digital design and high performance photonics. We believe that this is the first attempt in this direction focused on CMOS technology.

Near-Infrared Optical Tomography with Single-Photon Avalanche Diode Image Sensors

Juan Mata Pavia

In the past decades different methods based on magnetic resonance imaging (MRI) and positron emission tomography (PET) have been developed to image a variety of hemodynamic parameters in tissue. However, simultaneous high resolution imaging of oxy- and deoxyhemoglobin is not yet possible in clinical practices with millimeter accuracy. Near-infrared Spectroscopy (NIRS) is a well established technique that has been widely utilized in research and clinical practice to monitor the concentration of different chromophores in blood. It is capable of measuring a variety of parameters such as oxygenation levels in tissue, hematocrit, and cytochrome c oxidase levels among others. By increasing the amount and complexity of the light sources and detectors integrated in NIRS systems, in the last years researchers have been able to acquire tomographic images of such chromophores. This new imaging modality is known by different names: near-infrared optical tomography (NIROT), optical tomography (OT), diffuse optical tomography (DOT), or diffuse optical imaging (DOI). One of the main factors that limited the quality of the tomographic images obtained with NIROT has been the low number of sources and detectors employed in NIROT systems. The integration of the first single-photon avalanche diode (SPAD) together with time-to-digital converters (TDCs) in CMOS enabled a whole new range of possibilities in the field of single-photon detection. In this thesis the application of a SPAD-TDC image sensor in NIROT is presented for the first time. The main objective was to develop a new system that could perform acquisitions nearly in real time and that was capable of delivering tomographic images in a short period of time for medical evaluation. A new optical setup was conceived based on this detector to take advantage of the large amount of information delivered by the SPADs. By employing line-shaped illumination sources instead of point like sources, the target is more homogeneously illuminated and consequently a reduced number of sources is necessary. It was experimentally demonstrated that a resolution of 5 mm is possible with this new NIROT system. New algorithms that reduced the ill-posed nature of the image reconstruction problem were developed thanks to the wide-field time-resolved measurements delivered by the SPAD image sensors. The large datasets obtained with our NIROT system and its time-resolved capabilities enabled the development of fast methods capable of reconstructing an image with millimeter resolution in a few seconds with a laptop computer. We also analyze the effect of microlenses on the light sensitivity of the image sensor, showing that it is possible to increase it by a factor of 10 under certain conditions. A new image sensor with 4x400 pixels implemented in a 3D CMOS technology for NIROT applications is also presented. To our knowledge, this is the first backside illuminated SPAD array that incorporates in-pixel TDCs. A novel TDC architecture was introduced that reduces the energy consumed per conversion, consequently allowing a high number of TDCs working in parallel. The study of how NIROT can benefit from SPAD image sensors is presented in this thesis. Despite their current limitations, they enable the implementation of systems with thousands of detectors capable of millimeter resolution. Further developments in SPAD array architectures and TDCs will continue improving the performance of time-resolved NIROT systems.

EPFL2015

Arrays of Single Photon Avalanche Diodes in CMOS Technology: Picosecond Timing Resolution for Range Imaging (INVITED)

Pierre-André Besse, Edoardo Charbon, Cristiano Niclass

A solid-state imager fabricated in CMOS technology is presented for depth information capture of arbitrary 3D objects with millimeter resolution. The system is based on an array of 32x32 pixels that independently measure the time-of-flight of a ray of light as it is reflected back from the objects in a scene. A single cone of pulsed laser light illuminates the scene, thus no complex mechanical scanning is required. Millimetric depth accuracies can be reached thanks to the rangefinder’s optical detectors that enable picosecond time discrimination. The detectors, based on a single photon avalanche diode operating in Geiger mode, utilize avalanche multiplication to enhance light detection. Optical power requirements on the light source can therefore be significantly relaxed. A number of standard performance measurements, conducted on the imager, are discussed in this paper. The 3D imaging system was also tested on real 3D subjects demonstrating the suitability of the approach.

2005

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.