Publication

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Publications associées (86)

Graph Chatbot

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Connectez-vous pour utiliser Chat avec Graph Search

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

Growth of graded doped Si/SiGe Heterostructure Tunnel FET

Arnab Biswas

Tunnel FETs are the most promising ultra low power devices due to their potential of steeper subthreshold slopes and capability of using very low drive voltages. Switching is based on quantum mechanical band to band tunneling and no longer on thermal emiss ...

2013

Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor

Mihai Adrian Ionescu, Montserrat Fernandez-Bolanos Badia, Elizabeth Buitrago Godinez, Matthieu Berthomé

Silicon nanowire (SiNW) field effect transistors (FETs) have been widely investigated as biological sensors for their remarkable sensitivity due to their large surface to volume ratio (S/V) and high selectivity towards a myriad of analytes through function ...

Elsevier2013

Transient Off-Current in Junctionless FETs

Jean-Michel Sallese, Didier Bouvet, Farzan Jazaeri, Lucian Barbut

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Defect states characterization of non-annealed and annealed ZrO2/InAlN/GaN structures by capacitance measurements

Nicolas Grandjean, Jean-François Carlin

InAlN/GaN metal-oxide-semiconductor structures with non-annealed and annealed ZrO2 gate insulators were characterized by capacitance-voltage (C-V) measurements. A significant capacitance hysteresis in both channel depletion and barrier accumulation regions ...

Amer Inst Physics2013

Recent enhancements in BSIM6 bulk MOSFET model

Christian Enz, Yogesh Singh Chauhan, Maria-Anna Chalkiadaki

In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is i ...

2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors

Mihai Adrian Ionescu, Ji Cao

Self-aligned suspended-body single-walled (SW) carbon nanotube field-effect transistors (CNFETs) with dual lateral gates have been demonstrated. Two independent lateral gates are symmetrically placed less than 100 nm away from the CNT channel. The operatio ...

2012