Single-photon Avalanche Diodes in sub-100nm Standard CMOS Technologies

Single-photon avalanche diodes (SPADs) are evaluated in two sub-100nm CMOS technologies. Several geometries are implemented, whereas premature edge breakdown (PEB) prevention is achieved with n-well rings. The octagonal SPADs are implemented in 90nm and 65nm standard CMOS technologies. Full characterization of SPAD performance is carried out as a function of bias and temperature. To the best of our knowledge, this is the first report of SPAD in any 65nm CMOS technology.