Substrate Current Modeling for high Temperature Smart Power BCD Technology

The electronics industry is present nowadays in the most various applications. A new type of technology for integrated circuits named BCD has started to be developed and appeared from the mid 1980’s. This new technology allows integrating bipolar transistors, high voltage MOS transistors named DMOS and standard CMOS technologies on one substrate. This new technology used in integrated circuits is called Smart Power (Power & Intelligence). Before that, power integrated circuits were developed only with bipolar technologies. These technologies are perfectly suitable for analogue functions such as audio amplification or charge commutation, but are not dedicated to the integration of logical functions. The motor control industry has demanded more and more solutions for smart management of motors. Those solutions are used for power window lifts where the circuit receives commands through LIN bus present in automobiles and is able to manage the motor autonomously. This type of applications requires more and more digital functions within the circuit. Without the integration of CMOS technologies, the targets of costs and performances can be achieved only using many integrated circuits. This induces issues of reliability, electromagnetic compatibility and space. This is why the family of circuits called Smart Power combining power components as well as logical functions is unavoidable in that field. The most important problem of Smart‐Power circuits is the perturbations induced by power components within the circuit itself. Those parasitic effects can affect and disturb highly the functionality of the integrated circuit and can even destroy the circuit or its main functionalities. Nowadays, it is very difficult, even hardly possible to predict the noise within the circuit substrate using the same modeling techniques as the ones used for transistor modeling. This work presents a new modeling strategy based on equivalent schematic interconnecting simple modeling elements. The particularity of the proposed elements is that the two types of charge carriers are taken into account when interconnecting these elements. The correct physical modeling of these charge transport phenomenon taking place in the substrate is then guaranteed. The advantages of this modeling technique for an integrated circuit designer are its simplicity to be implemented as well as a very short calculation time. The developed method has been used to model parasitic effects present in an industrial circuit. The results obtained are compared to current calculation method, as well as to measurements.

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005

Substrate modeling of parasitic couplings in Smart Power ICs with generalized lumped devices

Camillo Stefanucci

Today automotive industry is demanding more and more compact solutions for embedded electronics to be interfaced with vehicles components such as motor drivers, igniters and car communication buses. That is why Smart Power Integrated Circuits (IC) have been developed where high voltage (HV) and low voltage electronics co-exist on the same chip. As a matter of fact, during the operation of HV transistors with inductive loads, electrons and/or holes are injected in the common silicon substrate. These carriers propagate through different wells and can be collected far away from the HV device. The generated parasitic currents can disturb sensitive analog circuits on the surroundings and many times they compromise the functionality of the entire chip. The failure mechanism is often described in terms of parasitic bipolar transistors activated by the injection of minority or majority carriers. However these parasitic devices are strongly dependent on the layout of the IC whereas their electrical characteristics are not known before the chip production. As a consequence, during the analog design flow there are no available solutions to simulate such substrate currents using modern Computer Aided Design (CAD) tools, and this leads to costly redesigns of Smart Power ICs. In this context, the objective of this research is to develop a general substrate modeling strategy to prevent these problems for whatever possible layout or electrical configuration. The proposed solution relies on the extraction of a parasitic distributed network to be simulated in standard circuit simulators. For that purpose three enhanced lumped components are developed: a diode that accounts for minority carriers injection, a resistor used to propagate carriers away in the substrate, and an homojunction that takes care about doping discontinuities effects. These devices are composed of two coupled circuits, the Total Current Circuit (TCC) and the Minority Carrier Circuit (MCC) and they include capacitive and high current effects. Moreover, the proposed modeling methodology can be further extended to other domains such as a self heating and Electrostatic Discharge (ESD) phenomena provided some extensions are done. Once properly calibrated with respect to a given HV technology process, the proposed substrate model has been proved to be effective to predict triggered parasitic current couplings in Smart Power ICs. As a consequence, new protection strategies can be developed to reduce unwanted parasitic effects. This new methodology and its inherent enhanced devices concept compatible with designers CAD tools opens new horizons for Smart Power ICs robust design.

EPFL2016

Substrate modeling of parasitic couplings in Smart Power ICs with generalized lumped devices

Camillo Stefanucci

EPFL2016

SOI mixed-mode design techniques and case studies

Marija Blagojevic

EPFL2005