Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding
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Hybrid integration and especially the packaging of microelectromechanical systems (i.e. MEMS) cannot rely on standardised packaging solutions due to the diversity of microsystems. As an example, the packaging requirements of a pressure sensor are different ...
Institut de Microtechnique, Université de Neuchâtel2009
Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint ...
Accurate statistical modeling and simulation are keys to ensure that integrated circuits (ICs) meet specifications over the stochastic variations inherent in IC manufacturing technologies. Backward propagation of variance (BPV) is a general technique for s ...
We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain seve ...
We demonstrate high-performance nanowire superconducting single photon detectors (SSPDs) on bN thin films grown at a temperature compatible with monolithic integration. NbN films ranging from 150nm to 3nm in thickness were deposited by dc magnetron sputter ...
In this paper we propose to eliminate all data and control pads generally present in conventional chips and to replace them with a new type of ultra-compact, low power optical interconnect implemented almost entirely in CMOS. The proposed scheme enables en ...
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...
This paper presents a modeling strategy to simulate 2D propagation of electrical perturbations induced by direct biasing of substrate junctions. Identifying parasitic substrate devices such as bipolar transistors reaches rapidly its limit when multiple cur ...
In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...
Capillary fluidic self-assembly (SA) intrinsically features massively-parallel, contactless die handling and allows for high-precision die placement. It may thus boost die-to-substrate assembly throughput and scalability. Here we characterize for the first ...