An ultra-low power energy-efficient microsystem for hydrogen gas sensing applications
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Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...
This paper discusses techniques, limitations and possible future developments of circuits based on transistors operated in the weak inversion (w.i.) mode, also called subthreshold mode. In analog circuits, w.i. is reached at very low current, but it is als ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009
Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing t ...
The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing ...
Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V-dd < V-th), one of the important consideration is to improve the energy ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011
The paper presents a programmable triangular neighborhood function for application in low power transistor level implemented Kohonen self-organized maps (SOMs). Detailed simulations carried out for the software model of such network show that the triangula ...
In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...
Institute of Electrical and Electronics Engineers2011
In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used in an analog-to-digital converter (ADC), it injects the spurious tones into the sampled data. These distortions ...
This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...
Integrated DNA-sensor arrays typically check for probe-target strand hybridization by analyzing the sensed capacitance changes, normally off-chip in software. However,many applications like portable medical devices require only the detection of an event or ...
