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High-Throughput Maps on Message-Passing Manycore Architectures: Partitioning versus Replication

Publications associées (34)

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Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

ACM2023

Asynchronous Simulation of Neuronal Activity

Bruno Ricardo Da Cunha Magalhães

Simulations of the electrical activity of networks of morphologically-detailed neuron models allow for a better understanding of the brain. Short time to solution is critical in order to study long biological processes such as synaptic plasticity and learn ...

EPFL2019

A Minimally Intrusive Low-Memory Approach to Resilience for Existing Transient Solvers

Allan Svejstrup Nielsen

We propose a novel, minimally intrusive approach to adding fault tolerance to existing complex scientific simulation codes, used for addressing a broad range of time-dependent problems on the next generation of supercomputers. Exascale systems have the pot ...

2019

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

EPFL2018

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

The increased number of cores integrated on a chip has brought about a number of challenges. Concerns about the scalability of cache coherence protocols have urged both researchers and practitioners to explore alternative programming models, where cache co ...

EPFL2015

High-Throughput Maps on Message-Passing Manycore Architectures: Partitioning versus Replication

André Schiper, Thomas Ropars, Omid Shahmirzadi

The advent of manycore architectures raises new scalability challenges for concurrent applications. Implementing scalable data structures is one of them. Several manycore architectures provide hardware message passing as a means to efficiently exchange dat ...

2014

The constant increase in single core frequency reached a plateau during recent years since the produced heat inside the chip cannot be cooled down by existing technologies anymore. An alternative to harvest more computational power per die is to fabricate ...

EPFL2014

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

2014