SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

This paper introduces SIMinG-1k-a manycore simulator infrastructure. SIMinG-1k is a graphics processing unit accelerated, parallel simulator for design-space exploration of large-scale manycore systems. It features an optimal trade-off between modeling accuracy and simulation speed. Its main objectives are high performance, flexibility, and ability to simulate thousands of cores. SIMinG-1k can model different architectures (currently, we support ARM (Available from: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0100i/index.html) and Intel x86) using two-step approac where architecture specific front end is decoupled from a fast and parallel manycore virtual machine running on graphical processing unit platform. We evaluate the simulator for target architecture with up to 4096 cores. Our results demonstrate very high scalability and almost linear speedup with simulation of increasing number of cores.

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

David Atienza Alonso, Luca Benini, Shivani Raghav, Martino Ruggiero

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available. General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach.

IEEE/ACM Press2011

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

David Atienza Alonso, Luca Benini, Shivani Raghav, Martino Ruggiero

Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, performance (and power) evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of 1,000-core future scenarios. The main contribution of this paper is the development of a simulator for 1,000-core processors which exploits the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected trough a Networkon- Chip (NoC). Our experiments confirm the feasibility of our approach. Currently, our ongoing work is focused on developing the power models within the simulation engine

2011

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predictions of design alternatives to prepare early software development and to assess the performance of a system before the real hardware is available. However, simulation technology for large-scale, many-core systems is lagging behind. Most of the existing simulation techniques are slow and complex or have poor scalability and high cost of development, which leads to an unacceptable performance when simulating a large number of cores. New challenges brought by emerging many-core systems demand new methods for simulating these platforms. This thesis investigates the techniques for improving the performance of parallel simulators to model many-core heterogeneous architectures. With the recent advances in programmability and processing power of graphical hardware, General Purpose Graphical Processing Units (GPGPUs) are becoming a popular host platform for solving broad range of computationally expensive problems. The easy availability of low cost, highly parallel GPGPU platforms presents an opportunity for accelerating architectural simulations. In this thesis, I propose and investigate a novel idea of using GPGPUs as a host platform for accelerating simulation of many-core systems. GPGPUs are most suitable for certain specific highly parallel workloads with fine-grained multi-threading and high computational intensity. Architectural simulation, on the other hand, is an extremely complex task with numerous dependencies and rules. To this end, I first determine the feasibility of accelerating various target many-core architectures at different levels of abstraction details, considering the particularities of prevalent GPU architectures and their programming models. Based on this study, I target a heterogeneous architecture of a multi-core CPU connected to many-core coprocessors for GPGPU acceleration. I propose ways to exploit ample parallelism in many-core simulation and present a comprehensive framework to develop an architecture-independent, fast, scalable, easy-to-use, full-system simulator. In particular, I outline some of the challenges faced and insights gained using our proposed approach. I present specific methods and approaches that maximize the throughput of GPU power and memory bandwidth allowing optimized parallelization with minimal synchronization. Our results show high scalability and high speed up in performance for simulating up to eight thousand cores.

EPFL2014

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

EPFL2014