Processeur graphique

Un processeur graphique, ou GPU (de l'anglais Graphics Processing Unit), également appelé coprocesseur graphique sur certains systèmes, est une unité de calcul assurant les fonctions de calcul d'image. Il peut être présent sous forme de circuit intégré (ou puce) indépendant, soit sur une carte graphique ou sur la carte mère, ou encore intégré au même circuit intégré que le microprocesseur général (on parle d'un SoC lorsqu'il comporte toutes les puces spécialisées). Dans la terminologie d'AMD un GPU intégré à la même puce que le processeur est appelé APU, et dans la terminologie d'Intel un IGP). La sortie peut être affichée à l'écran, ou retraité en RAM ou VRAM pour différents usages, telle que l'écriture sur mémoire de masse ou un nouveau traitement interne. Un processeur graphique a généralement une structure hautement parallèle (voir accélération matérielle) qui le rend efficace pour une large palette de tâches graphiques comme le rendu géométrique 2D ou 3D, s'opérant généralement d

Graph Signal Processing

Ntorina Thanou

Over the past few decades we have been experiencing an explosion of information generated by large networks of sensors and other data sources. Much of this data is intrinsically structured, such as traffic evolution in a transportation network, temperature values in different geographical locations, information diffusion in social networks, functional activities in the brain, or 3D meshes in computer graphics. The representation, analysis, and compression of such data is a challenging task and requires the development of new tools that can identify and properly exploit the data structure. In this thesis, we formulate the processing and analysis of structured data using the emerging framework of graph signal processing. Graphs are generic data representation forms, suitable for modeling the geometric structure of signals that live on topologically complicated domains. The vertices of the graph represent the discrete data domain, and the edge weights capture the pairwise relationships between the vertices. A graph signal is then defined as a function that assigns a real value to each vertex. Graph signal processing is a useful framework for handling efficiently such data as it takes into consideration both the signal and the graph structure. In this work, we develop new methods and study several important problems related to the representation and structure-aware processing of graph signals in both centralized and distributed settings. We focus in particular in the theory of sparse graph signal representation and its applications and we bring some insights towards better understanding the interplay between graphs and signals on graphs. First, we study a novel yet natural application of the graph signal processing framework for the representation of 3D point cloud sequences. We exploit graph-based transform signal representations for addressing the challenging problem of compression of data that is characterized by dynamic 3D positions and color attributes. Next, we depart from graph-based transform signal representations to design new overcomplete representations, or dictionaries, which are adapted to specific classes of graph signals. In particular, we address the problem of sparse representation of graph signals residing on weighted graphs by learning graph structured dictionaries that incorporate the intrinsic geometric structure of the irregular data domain and are adapted to the characteristics of the signals. Then, we move to the efficient processing of graph signals in distributed scenarios, such as sensor or camera networks, which brings important constraints in terms of communication and computation in realistic settings. In particular, we study the effect of quantization in the distributed processing of graph signals that are represented by graph spectral dictionaries and we show that the impact of the quantization depends on the graph geometry and on the structure of the spectral dictionaries. Finally, we focus on a widely used graph process, the problem of distributed average consensus in a sensor network where sensors exchange quantized information with their neighbors. We propose a novel quantization scheme that depends on the graph topology and exploits the increasing correlation between the values exchanged by the sensors throughout the iterations of the consensus algorithm.

EPFL2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Andreas Peter Burg, João Maria Duarte Andrade, Gabriel Falcao Paiva Fernandes, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

Assoc Computing Machinery2015

Graph Signal Processing

Ntorina Thanou

EPFL2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Andreas Peter Burg, João Maria Duarte Andrade, Gabriel Falcao Paiva Fernandes, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna

Assoc Computing Machinery2015

A VLSI processor architecture for professional digital audio

Graph Signal Processing

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Graph Signal Processing

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

A VLSI processor architecture for professional digital audio