A 15 mu W 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB
Graph Chatbot
Chattez avec Graph Search
Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.
AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.
This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimental flex ...
In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner t ...
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
This paper presents a new two-sections architecture of a low power switched capacitor (SC) finite impulse response (FIR) filter suitable for base-band signal processing in WCDMA and in GSM standards. The low power operation is possible due to several optim ...
The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...
An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for Wireless Sensor Network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data p ...
An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modula ...
A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tune ...
This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme is based on Brun's algorithm for finding integer relations. We analyze its high-level ar ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007
This paper presents the modeling and design methods of true-time distributed microelectromechanical systems transmission lines (DMTLs) making use of periodic structure theory. New contributions to the analysis and reduction of the microelectromechanical sy ...