Publication
Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energy-efficient computing systems. However, it comes at the cost of increased sensitivity to soft errors. To address this issue, bit-interleaving SRAM is widely used to mitigate soft errors. But it suffers from halfselect disturbance. Previous works address such disturbance by using a dedicated write port or enhanced write assist scheme. However, these works may decrease write margin, induce high cell-level write latency, or incur architecture-level time/timing overhead. In this paper, we develop a high-speed bit-interleaving half-select disturb-free memory with data-aware 10T SRAM. First, we present an isolated and decoupled topology with dedicated write control to improve stability. Second, we present a data-aware write path with enhanced write-ability that effectively reduces the write access time. A 40-nm 4-Kb test chip has been fabricated to validate the optimizations above. Measurement results show that our half-select disturb-free test chip achieves a peak operating frequency of 25 MHz and an energy consumption of 0.168 fJ/bit with a supply voltage of 0.35 V. Compared with the state-of-the-art designs, it has achieved a speed up of 2.72× and an energy saving of 93.8%.