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A CMOS compatible Ge avalanche photodiode is fabricated on Si by using a selective chemical-vapor deposition (CVD) epitaxial growth technique. At a temperature of 700°C, single crystal islands of As-doped Ge are grown in windows to the Si with sizes up to ...
Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...
Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...
An important prerequisite for the design of digital integrated circuits is the ability to control the threshold voltage of the individual transistors during manufacturing. To address the problem of controlling the threshold voltage of low-voltage organic t ...
This thesis aims at the site-specific realization of self-assembled field-effect transistors (FETs) based on semiconducting Zinc oxide NWs and their application towards chemical and bio-sensing in liquid medium. At first, a solution based growth method for ...
In this letter, we report the performance of high-kappa/metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage ...
Based on a detailed study of the radiation tolerance of high-voltage transistors, 2 commercial CMOS technologies have been selected for the design of synchronous buck DCDC converter ASICs. Three prototype converters have been produced, embedding increasing ...
In the past, tantalum oxide devices have been used to create non-volatile digital memories, whilst neglecting the analogue memristive characteristics of such devices. In this Letter, it is shown that these devices can provide a low-cost, low-power solution ...
The paper presents a new CMOS implementation of the initialization mechanism for Kohonen self-organizing neural networks. A proper selection of initial values of the weights of the neurons exhibits a significant impact on the quality of the learning proces ...
Presented is a transistor-level implementation of a floating and tunable CMOS active inductor. It is based on the classical gyrator-C topology and is enhanced by adding an internal offset reduction mechanism to guarantee functionality also for unbalanced D ...