DFT-based synchrophasor estimation processes for Phasor Measurement Units applications: algorithms definition and performance analysis

Among the various logical components of a phasor measurement unit (PMU), the synchrophasor estimation (SE) algorithm definitely represents the core one. Its choice is driven by two main factors: its accuracy in steady state and dynamic conditions as well as its computational complexity. Most of the SE algorithms proposed in the literature are based on the direct implementation of the Discrete Fourier Transform (DFT). This is due to the relatively low computational complexity of such technique and to the inherent DFT capability to isolate and identify the main tone of a discrete sinusoidal signal and to reject closeby harmonics. Nevertheless, these qualities come with non-negligible drawbacks and limitations that typically characterize the DFT: mainly they refer to the fact that the DFT theory assumes a periodic signal with time-invariant parameters, at least along the observation window. The latter, from one side should be as short as possible to be closer to the above-mentioned quasi-steady-state hypothesis also during power system transient; on the other hand, longer windows are needed when interested in rejecting and isolating harmonic and inter-harmonic signals that are quite frequent in power systems. In this respect, this chapter first analyses the DFT with a particular focus on the origin of the well-known aliasing and spectral leakage effects. Then it formulates and validates in a simulation environment a novel SE algorithm, hereafter referred as iterative-Interpolated DFT (i-IpDFT), which considerably improves the accuracies of classical DFT- and IpDFT-based techniques and is capable of keeping the same static and dynamic performances independently of the adopted window length that can be reduced down to two cycles of signal at the nominal frequency of the power system. This chapter is organized as follows: Section 3.2 introduces the nomenclature and some basic concepts in the field of synchrophasors. Section 3.3 presents the theoretical background of the DFT, with a specific focus on the detrimental effects of aliasing and spectral leakage. Next, Section 3.4 discusses advantages and drawbacks of DFT-based SE algorithms and derives the analytical formulation of the i-IpDFT method. Finally, Section 3.5, after illustrating the procedure presented in Reference 1 to assess the performances of a PMU, analyses the performances of the i-IpDFT algorithm using two of the testing conditions presented in Reference 1 and compares them with those of the classical IpDFT technique.

Algorithms for the Computation of Continuous Transforms of Rectilinear Polygons from IC Layouts

Robin Scheibler

In this work, we present a novel way of computing the continuous Haar, Fourier and cosine series coefficients of rectilinear polygons. We derive algorithms to compute the inner products with the continuous basis functions directly from the vertices of the polygons. We show that the overall computational complexity of those algorithms is lower than that of the traditional corresponding discrete transforms when the number of vertices is small, in addition to sparing the memory needed for a discrete image. This makes those continuous transforms particularly suitable for applications in Computational Lithography (CL) where speed and memory are critical requirements. We validate the presented algorithms through an implementation in a CL software under development at the IBM Zurich Research Laboratory and benchmark against discrete state of the art transforms on real Integrated Circuit (IC) layouts. Finally, we measure the approximation power of the Haar transform when applied to rectilinear polygons from IC layouts in order to evaluate its potential for pattern matching applications.

2009

Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype

Mario Paolone, Paolo Romano

The literature on the subject of synchrophasor estimation (SE) algorithms has discussed the use of interpolated discrete Fourier transform (IpDFT) as an approach capable to find an optimal tradeoff between SE accuracy, response time, and computational complexity. Within this category of algorithms, this paper proposes three contributions: 1) the formulation of an enhanced-IpDFT (e-IpDFT) algorithm that iteratively compensates the effects of the spectral interference produced by the negative image of the main spectrum tone; 2) the assessment of the influence of the e-IpDFT parameters on the SE accuracy; and 3) the discussion of the deployment of IpDFT-based SE algorithms into field programmable gate arrays, with particular reference to the compensation of the error introduced by the free-running clock of A/D converters with respect to the global positioning system (GPS) time reference. The paper finally presents the experimental validation of the proposed approach where the e-IpDFT performances are compared with those of a classical IpDFT approach and to the accuracy requirements of both P and M-class phasor measurement units defined in the IEEE Std. C37.118-2011.

Institute of Electrical and Electronics Engineers2014

An enhanced interpolated-modulated sliding DFT for high reporting rate PMUs

Mario Paolone, Paolo Romano

The field of application of Phasor Measurement Units (PMUs) might be limited by the PMU measurements reporting latencies and achievable reporting rates, particularly with respect to power system protection applications that typically require very low latencies. A way to speed-up synchrophasor estimation algorithms based on the use of the Discrete Fourier Transform (DFT) refers to the usage of stable and accurate recursive processes for the DFT estimation. In this respect, this paper presents a synchrophasor estimation algorithm, called Interpolated-Modulated Sliding DFT (IpMSDFT), characterized by high accuracies and reduced latencies, enabling reporting rates up to thousands of synchrophasor per second. It is composed by two stages: (i) a guaranteed-stable technique for sample-by-sample DFT computation; (ii) an enhanced version of the classical IpDFT algorithm for synchrophasor estimation. The algorithm is analytically formulated and its digital design tailored to allow a feasible deployment on an FPGA-based PMU. The IpMSDFT-based PMU is finally validated with respect to the numerical stability of the proposed solution, its reporting latencies and the achievable reporting rates.

2014