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Digital signal processors are ubiquitous in electronics, with applications ranging from sound processing to software-defined radio. Finite impulse response (FIR) filters are among the components that are used for the processing; the implementation is tailored to the user’s needs, whether they specifically need performance or configurability. Handling numerous channels in a single filter block can be achieved in hardware by running multiple filters in parallels, with a high space expense and controller overhead. This project proposes and discusses an implementation template for a pipeline that simultaneously processes a desired number of channels, while keeping coefficients configurability. The implementation we propose is economic in terms of area while meeting the theoretical timing requirements to process long filters.
Mahsa Shoaran, Uisub Shin, Bingzhao Zhu