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Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Publications associées (32)

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Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for three-dimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technolo ...

2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

2022

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

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The soaring demand for computing power in our digital information age has produced as collateral undesirable effect a surge in power consumption and heat density for computing servers. Accordingly, 30-40% of the energy consumed in state-of-the-art servers ...

IEEE/ACM Press2014

Numerous Directed-Acyclic Graph (DAG) schedulers have been developed to improve the energy efficiency of various multi-core systems. However, the DAG monitoring modules proposed by these schedulers make a priori assumptions about the workload and relations ...

2014

A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers

David Atienza Alonso, Karim Kanoun

IEEE2014

A Fully Integrated 0.18-um CMOS Transceiver Chip for X-Band Phased-Array Systems

Kiarash Gharibdoust

An X-band core chip is designed and fabricated in 0.18-um CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, ...

Institute of Electrical and Electronics Engineers2012

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Transactional memory is an appealing paradigm for concurrent programming. Many software implementations of the paradigm were proposed in the last decades for both shared memory multi-core systems and clusters of distributed machines. However, chip manufact ...

2012

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

Ciprian Seiculescu

As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor ...

EPFL2012