Piezoresistivity characterization of silicon nanowires through monolithic MEMS

This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-μm-thick MEMS on the same silicon-on-insulator (SOI) wafer. MEMS is designed in the form of a characterization platform with an electrostatic actuator and a mechanical amplifier spanned by a single Si NW. This integrated platform is utilized for the successful measurement of Si NW piezoresistive gauge factor (GF) under a uniform uniaxial stress. Available techniques in this field include: Indirect (substrate) or direct (actuator) bending of Si NW necessitating rigorous models for the conversion of load to stress, inanomanipulation and attachment of Si NW on MEMS, a non-monolithic technique posing residual stress and alignment issues, and heterogeneous integration with separate Si layers for Si NW and MEMS, where a single SOI is not sufficient for the end product. Providing a monolithic solution to the integration of micro and nanoscale components, the presented technique successfully addresses the shortcomings of similar studies. In addition to providing a solution for electromechanical characterization, the technique also sets forth a promising pathway for multiscale, functional devices produced in a batch-compatible fashion, as it facilitates co-fabrication within the same Si crystal.

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

Yusuf Leblebici, Davide Sacchetto, Izzet Yildiz

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-polishing-based metal electrode/contact formation. Nanowires up to a length of 50 mu m are achieved while retaining submicron nanowire-to-electrode gaps. The scalability of the technique is demonstrated through using no patterning method other than optical lithography on conventional SOI substrates. Structural integrity of double-clamped nanowires is evaluated through a three-point bending test, where good clamping quality and fracture strengths approaching the theoretical strength of the material are observed. Resulting devices are characterized in resonator and switch applications-two areas of interest for CMOS-compatible solutions-with all-electrical actuation and readout schemes. Improvements and tuning of obtained performance parameters such as resonance frequency, quality factor and pull-in voltage are simply a question of conventional design and process adjustments. Implications of the proposed technique are far-reaching including system-level integration of either single-nanowire devices within thick Si layers or nanowire arrays perpendicular to the plane of the substrate.

Institute of Physics2011

A Monolithic Approach to Downscaling Silicon Piezoresistive Sensors

Yusuf Leblebici, Mohammad Nasr Esfahani

Multi-scale integration remains the primary challenge in the fabrication of miniature piezoresistive sensors, as the co-fabrication of a silicon nanowire along with a microscale shuttle is the main architecture facilitating high-sensitivity transduction. The efforts in this field are marred by the lack of batch techniques compatible with semiconductor manufacturing. A technology is introduced here that leads to the fabrication of a piezoresistive silicon nanowire sharing the same single-crystalline device layer of a thick silicon-on-insulator wafer as the microscale component. The approach is based on a combination of high-resolution lithography with a two-stage etching process. The demonstration is carried out by spanning an electrostatic comb-drive actuator and a micromechanical amplifier by a single nanowire. A gage factor range of 135-145 is obtained, corresponding to an almost 20% resistance change for a nanowire strain of 1.26 x 10(-3). The technique is shown to generate a two-order-of-magnitude scale difference within the same silicon crystal. It also provides ease of electrical access to the nanowire, as the nanowire does not remain buried underneath the thick micromechanical system. With the associated lack of high-temperature processes and its CMOS-compatibility, the technique is a promising enabler for future miniaturized piezoresistive sensors. [2017-0007]

Institute of Electrical and Electronics Engineers2017

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Georg Fantner, Yusuf Leblebici, Oliver Peric, Davide Sacchetto, Zuhal Tasdemir

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures down, leading to higher performance devices.Even though there are some techniques which use bottom-up approach, the resulted structures suffer from the alignment and manipulation (pick and place) issues making a reliable integration even more difficult to achieve due to interfacing problems. In order to eliminate assembly issues, the limits of the conventional micro/nano-fabrication processes should be addressed and further studied. In addition, the use of single-crystal silicon in conventional micro/nano-fabrication processes gives the advantage of improved mechanical performance thanks to the lack of impurities and crystallographic defects as compared to their bottom-up counterparts.In this study, we exploit the approach of the well-known micromachining process called SCREAM (Single Crystal Reactive Etching and Metallization). Si NW is patterned on the silicon wafer by using e-beam lithography. Conventional reactive ion etching is then used to both suspend the patterned nanowire along with etching whole silicon surface, which will form the rest of the microscale device.

2014