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Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Publications associées (49)

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Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

EPFL2021

Micro-architectural Analysis of Database Workloads

Utku Sirin

Database workloads have significantly evolved in the past twenty years. Traditional database systems that are mainly used to serve Online Transactional Processing (OLTP) workloads evolved into specialized database systems that are optimized for particular ...

EPFL2021

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

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Ultrafast ultrasound (US) imaging uses unfocused waves to insonify the whole medium of interest at once, allowing pulse-echo US imaging to achieve very high frame rates, at the cost of a lower image quality. In this paper, we present USSR, an UltraSound Sp ...

Ieee2017

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

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Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...

2015