Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâs law. Modern digital integrated circuits contain billions of transistors, fabricated with CMOS technology. As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. Among the materials that are studied for charge-based devices, two-dimensional materials of the Transition Metal Di-Chalcogenides (TMDCs) family show promising opportunities, thanks to their electrical and physical properties. In order to enable 2D electronics to be integrated in the Back-End-Of-the-Line (BEOL) with conventional CMOS it is essential to attain complementary operation of the transistors, in order to achieve low standby power consumption. In CMOS, ions are physically implanted in silicon to create unipolar devices with Ohmic contacts. However, this process requires high annealing temperatures, which are not compatible with the low-thermal budget requirements for monolithic 3D integration. For 2D materials, physical doping, through ion-implantation, has not proven to be successful due to extreme thinness of the 2D semiconductors. The possibility of introducing dopant atoms during growth of the 2D material has been reported, but does not allow for any control of the doping profile. Several chemical and molecular doping techniques have been developed, but are non-stable and non-CMOS compatible. A device concept that does not rely on any physical or chemical doping, and use instead un-doped materials, would be of great interest in this regard. In this thesis, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer tungsten di-selenide. We show how modulation of the Schottky barriers at drain and source by a separate gate, named polarity gate, can enable the selection of the carriers injected in the channel, and achieve controllable polarity behaviour with ON/OFF current ratios > 1E6 for both electrons and holes conduction. Following this demonstration, we fabricate and characterize a variety of polarity-controllable logic gates such as Inverter, NAND, NOR, that are the building primitives used in the logic synthesis frameworks for conventional CMOS logic. Moreover, we experimentally show 2- and 3-Input XOR, and majority gates that, thanks to the polarity-controllable devices, can be realized with fewer transistors as compared to what is achievable in conventional CMOS. We demonstrate a complete standard cell library with the possibility of fabricating compact, highly-expressive logic gates that can be exploited to gain advantages at circuit level, using XOR and MAJ functions as logic primitives. Moreover, for the first time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono and bi-layer 2D materials. Using ballistic self-consistent quantum simulations combined with TCAD simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to sub-10nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices.

A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications.

Matthias Neuenschwander

The field of micro electromechanical systems (MEMS) evolved from the microelectronic industry and the technologies developed to fabricate integrated circuits. As a result, MEMS are commonly fabricated on silicon wafers. The development of MEMS has been driven by three main merits: miniaturisation, microelectronics integration, and parallel fabrication with high precision. Many operational properties scale well with smaller sizes. In addition, integrated electronic circuitry allows embedding MEMS with computing or networking capabilities, while parallel manufacturing enables the fabrication of many identical devices on a single wafer, reducing the unit cost. The main MEMS application is transducers which transform signals from one form of energy to another, and can be used for perception (sensors) or to produce actions (actuators). Silicon and other microelectronic materials like metals have enabled very high-performance MEMS transducers because these materials can be used for a range of very effective actuating and sensing principles.More recently, polymers have started to be used in MEMS because of their unique electrical, physical and chemical properties which include biocompatibility, viscoelasticity and mechanical shock tolerance. They are also much softer than silicon or metals, and they can be processed using many techniques that allow unique low-cost, batch-style fabrication and packaging. However, polymers have relatively low glass-transition and melting temperatures. As a result, the advantages of polymers cannot easily be combined with high-performance actuating and sensing elements as these are based on silicon technology and require high-temperature fabrication steps. Here, a hybrid-MEMS fabrication process is used to address this issue. The developed devices are based on a trilayer structure, where a thick polymer core is sandwiched between two hard thin films, while electronic layers are embedded within in a fluid-compatible way.The objective of this thesis is to turn hybrid-MEMS into a benchmark MEMS technology. This involves many different aspects. First, sensing and actuation elements are integrated into trilayer devices, and their performance is analysed. Then, some more unique possibilities offered by hybrid-MEMS are exploited. A way to fabricate electronics on multiple layers is developed, which allows different electronic features to be integrated in parallel. In addition, three-dimensional bulk features fabricated at several levels are demonstrated. This is possible because the hybrid-MEMS process is based on the bonding of multiple wafers.All these new fabrication features are demonstrated in atomic force microscopy (AFM) applications. Self-actuated trilayer AFM cantilevers with sharp silicon tips are used to boost imaging speeds in the off-resonance tapping (ORT) mode, thanks to an order of magnitude faster surface probing rates. Furthermore, fully integrated ORT imaging is demonstrated with self-actuated piezoresistive cantilevers. Next, trilayer cantilevers with shielded conductive tips are introduced for electrical AFM modes. Finally, ongoing research projects are touched upon, including approaches to fabricate hybrid-MEMS with single crystal silicon piezoresistors for improved sensitivity, and an analysis of reproducibility of fabricated trilayer cantilevers.

EPFL2022

Graphene Field Effect Devices and Circuits

Clemens Benedict Nyffeler

Electronics today permeate our life and existence. It has become nearly impossible to evade any dependence on electronic devices that surround us every day - computers, phones, televisions. But also other objects become increasingly "smart" - watches, cars, coffee machines, even entire buildings. Without necessarily being aware of it, every person in our modern world is the owner of billions, probably tens of billions of transistors. These elementary switches are the primitive units, of which all electronic devices are made, much like biological cells constitute our bodies. Decades of technological progress at an incredible pace have been fueled by the constant improvement of semiconductor device technology. The original combination of silicon, silicon dioxide and aluminum required to build a transistor, has been complemented by a myriad of other materials. One of the last remainders of the original technology, the silicon channel, is now about to be replaced as well. While a short term remedy for the next performance bottleneck might be found in III-V compounds a more compelling alternative could be found in 2D materials. Graphene was not only the first 2D material to be discovered and isolated in 2004, but also has the most extraordinary electric properties, owing to the high symmetry of its lattice. The content of this thesis presents a broad examination of the graphene field effect device reaching from the fabrication over electrical characterization to data analysis, device modeling and finally simulation of a small circuit. In this thesis, we present practical considerations regarding the experimental examination of graphene field-effect devices. A fabrication flow tailored for top-gated graphene devices was developed, taking into account the particular requirements and sensitivities of the material. We also describe a set of versatile software tools that were developed for the design of devices, chips and wafers, their automated electric characterization and finally for browsing and visualizing the measurement results. The data analysis was performed with a very effective conductance-based model, which is based on semi-empirical models commonly used to describe graphene devices. We provide an overview of these models, the phenomena which they take into account and the steps that can be taken to improve their accuracy to obtain the model we finally utilized. A environment was created to use our model in a \textsc{Spice}-like circuit simulator in order to study possible topologies in which graphene devices could constitute an elementary circuit block. We focus our study on devices that operate as a differential pair, resembling the configuration that also enables very high-speed source-coupled and emitter-coupled logic circuits based on standard silicon transistors. Using analytical calculations we determine tuning parameters and their optimum values to maximize the transfer characteristics of our graphene-based differential circuit block. In order to achieve more accurate simulation and as a means to verify the empirical model, we worked on a more rigorous approach. Based on first principles, we construct a model building on the specific carrier statistics in graphene. These deviate from the usual Boltzmann statistics and lead to a an equation describing the device's charge-voltage relation, which is transcendental and cannot ordinarily be solved. By using asymptotic approximations, we obtain closed-form expressions for the device current as a function of bias conditions. Unlike many other models, we can discriminate both between electron and hole currents as well as between drift and diffusion currents, making the model well-suited for implementation as a compact model.

EPFL2016

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005