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CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Publications associées (34)

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Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

An Analytical Model of Hardware Transactional Memory

Willy Zwaenepoel, Paolo Romano, Diego Didona

This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in ...

2017

Neural assemblies as core elements for modeling neural networks in the brain

Hesam Setareh

How does the brain process and memorize information? We all know that the neuron (also known as nerve cell) is the processing unit in the brain. But how do neurons work together in networks? The connectivity structure of neural networks plays an important ...

EPFL2017

Leveraging a Cluster-Booster Architecture for Brain-Scale Simulations

Felix Schürmann, James Gonzalo King, Michael Lee Hines, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko

The European Dynamical Exascale Entry Platform (DEEP) is an example of a new type of heterogeneous supercomputing architecture that include both a standard multicore-based "Cluster" used to run less scalable parts of an application, and an Intel MIC-based ...

Springer Int Publishing Ag2016

Simulation Neurotechnologies for Advancing Brain Research: Parallelizing Large Networks in NEURON

Felix Schürmann, Michael Lee Hines

Large multiscale neuronal network simulations are of increasing value as more big data are gathered about brain wiring and organization under the auspices of a current major research initiative, such as Brain Research through Advancing Innovative Neurotech ...

Mit Press2016

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâs future control flow and provide the core with a useful instruction stream to execute in ...

EPFL2015

On the Performance of Delegation over Cache-Coherent Shared Memory

André Schiper, Thomas Ropars, Darko Petrovic

Delegation is a thread synchronization technique where access to shared data is performed through a dedicated server thread. When a client thread requires shared data access, it makes a request to a server and waits for a response. This paper studies deleg ...

2015