A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Maher Kayal, François Krummenacher, Evgenia Voulgari
IEEE, 2019
Article de conférence

Résumé

An application specific integrated circuit (ASIC) named ANTIGONE (ANalog To dIGital cONvErter) was designed in AMS 0.35 mu m technology to interface with four Ion-sensitive field-effect transistor (ISFET) sensors and perform real-time monitoring of some biomarkers in human sweat. The non-invasive sweat sensing system is targeted for wearable personalized medicine and healthcare applications. The ASIC is based on the current-to-frequency converter (CFC) architecture and is able to perform measurements of multiple currents from a few pA up to 500 nA in time multiplexing. The ASIC is designed for low power consumption and interfaces with the sensors, biases them to the required voltages and sends the measured current values through a Serial Peripheral Interface (SPI) to a portable device.

Official source

https://infoscience.epfl.ch/record/273473?ln=fr

À propos de ce résultat

Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.

Concepts associés

Chargement

Publications associées

Chargement

, ,

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically designed to interface with multiple Ion-Sensitive Field-Effect Transistors (ISFETs) and detect biomarkers like pH, Na+, K+ and Ca2+ in human sweat. The ISFET-ASIC system can allow real-time noninvasive and continuous health monitoring. The ANTIGONE ASIC architecture is based on the current-to-frequency converter through the charge balancing principle. The same front-end can digitize multiple currents produced by four sweat ISFET sensors in time multiplexing. The front-end demonstrates good linearity over a dynamic range that spans from 1 pA up to 500 nA. The consumed energy per conversion is less than 1 J. The chip is programmable and works in eight different modes of operation. The system uses a standard Serial Peripheral Interface (SPI) to configure, control and read the digitally converted sensor data. The chip is controlled by a portable device over Bluetooth Low Energy (BLE) through a Microcontroller Unit (MCU). The sweat sensing system is part of a bigger wearable platform that exploits the convergence of multiparameter biosensors and environmental sensors for personalized and preventive healthcare

2021

Chargement

Design of an Energy-Efficient Current-to-Frequency Converter for a Wearable Sensor Platform

Maher Kayal, François Krummenacher, Evgenia Voulgari

This paper presents the design of the ANTIGONE ASIC in AMS 0.35 mu m technology that interfaces with ion-sensitive field effect transistors (ISFETs) to detect biomarkers like pH, Na+ and K+ in human sweat. The ISFET sensors generate a low current dc signal, so a current-to-frequency converter (CFC) architecture is used to measure the produced current of the different sensors in time multiplexing. The ASIC has to properly bias the ISFETs and send the digitized output signal to a microcontroller through an SPI interface. In the front-end, a switched capacitor circuit is used to balance the charge that is stored in the current integrator. The 12-bit converter is designed for low power consumption. The weak inversion region of operation is exploited to achieve the highest gain for the same power budget. The different analog blocks are following a power activation sequence in order to limit the power consumption during the idle states of the system.

IEEE2019

Chargement

An 8-bit low-power ADC array for CMOS image sensors

Michael Ansorge, Alexander Heubi, Steve Tanner

The paper presents an original analog-to-digital converter (ADC) array meeting the constraining requirements in resolution, speed, size, and low power consumption of high-performance low-cost video cameras. The converter array is based on ADC cells relying on a cyclic redundant signed digit (RSD) algorithm supporting comparators with extended tolerance. A prototype ADC array composed of 32 converters was integrated in a 1 μm CMOS process and tested. It is featuring an 8 bit resolution for an active area of 2.1 mm2, and a power consumption of 4 mW at a sampling rate of 4.2 MS/s, with a voltage supply of 2.6 V. Typical DNL and INL values of -0.5/+0.2 and ±0.4 LSB, respectively, were measured for each ADC cell. Moreover, an overall SNR of 45 dB can be achieved with a digital off-chip offset compensation.

1998

Chargement