Publication
SpecROP: Speculative Exploitation of ROP Chains
Publications associées (34)
How to Stop Under-Utilization and Love Multicores
Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis, Erietta Liarou
Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...
2015Shared Frontend for Manycore Server Processors
Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâs future control flow and provide the core with a useful instruction stream to execute in ...
EPFL2015Hierarchical Cycle Accounting: A New Method for Application Performance Tuning
Willy Zwaenepoel, Andrzej Pawel Nowak
To address the growing difficulty of performance debugging on modern processors with increasingly complex micro-architectures, we present Hierarchical Cycle Accounting (HCA), a structured, hierarchical, architecture-agnostic methodology for the identificat ...
2015Confluence: unified instruction supply for scale-out servers
Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak
Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...
ACM Press2015Code-Pointer Integrity
George Candea, Mathias Josef Payer, Volodymyr Kuznetsov
Systems code is often written in low-level languages like C/C++, which offer many benefits but also delegate memory management to programmers. This invites memory safety bugs that attackers can exploit to divert control flow and compromise the system. Depl ...
2014A Primer on Hardware Prefetching
Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...
Morgan & Claypool2014Transactions Chasing Scalability and Instruction Locality on Multicores
For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...
EPFL2014Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis
According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...
EPFL2013An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
David Atienza Alonso, Andreas Peter Burg, Pascal Andreas Meinerzhagen, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan, Oskar Andersson
Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often u ...
Springer2013An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks
Paolo Ienne, Ali Galip Bayrak, Wayne Burleson, Nikola Velickovic
Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leak ...
2012