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Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Publications associées (35)

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Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

Wladyslaw Grabinski, Antonios Bazigos, Matthias Bucher

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to incon ...

2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

Katherine Boucart

The down-scaling of conventional MOSFETs has led to an impending power crisis, in which static power consumption is becoming too high. In order to improve the energy-efficiency of electronic circuits, small swing switches are interesting candidates to repl ...

EPFL2010

The high-mobility bended n-channel silicon nanowire transistor

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis, Mohammad Najmzadeh

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

Institute of Electrical and Electronics Engineers2010

Selective Redundancy-Based Design Techniques for the Minimization of Local Delay Variations

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy app ...

IEEE Service Center2010

Energy efficiency enhancement of sub-threshold digital CMOS

Omer Can Akgun

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing ener ...

EPFL2009

Phase–frequency detecting time-to-digital converter

Kyojin Choo

A simple time-to-digital converter (TDC), capable of detecting not only phase difference but also frequency difference, is presented. The proposed TDC guarantees pull-in even for PLLs with the lowest loop gain. The TDC is fabricated in a 65 nm CMOS process ...

2009