Enhancement-mode Multi-channel AlGaN/GaN Transistors with LiNiO Junction Tri-Gate

Multi-channel GaN power device, consisting of stacking multiple two-dimensional-electron-gas (2DEG) channels, has been demonstrated to achieve unprecedented on-state performance while maintaining high breakdown voltage (VBR). However, the large carrier density (Ns) makes it more challenging to achieve high positive threshold voltages (VTH) on multi-channel epitaxies. In this work, we demonstrate enhancement-mode (e-mode) multi-channel GaN transistors based on conformally deposited p-type LiNiO over tri-gates to form a multi-channel junction gate structure. Compared to the normal MOS gate, the p-type LiNiO junction gate provides an additional depletion of the channels to yield a more positive VTH, reaching a maximum VTH of 1.2 V (defined at 1 μA/mm). Moreover, high-quality LiNiO provided excellent on-state performance in multi-channel tri-gate devices with a stable operation at high temperature, which present small VTH shift and hysteresis, and low off-state leakage current. The e-mode devices in this work presented a small specific RON (RON, sp) of 0.62 mΩ∙cm-2 along with a hard breakdown voltage (VBR) of 920 V. This work demonstrates the potential of LiNiO for high-performance e-mode power devices.

Ferroelectric transistors with improved characteristics at high temperature

Didier Bouvet, Mihai Adrian Ionescu, Livio Lattanzio, Giovanni Antonio Salvatore, Nava Setter, Igor Stolichnov

We report on the temperature dependence of ferroelectric metal-oxide-semiconductor (MOS) transistors and explain the observed improved characteristics based on the dielectric response of ferroelectric materials close to the Curie temperature. The hysteretic current-voltage static characteristics of a fully depleted silicon-on-insulator transistor, with 40 nm vinylidene fluoride trifluorethylene, and 10 nm SiO2 gate stack, are measured from 300 to 400 K. In contrast with conventional MOS field effect transistors (MOSFETs), the subthreshold swing and the transconductance show, respectively, a minimum and a maximum near the Curie temperature (355 K) of the ferroelectric material. A phenomenological model is proposed based on the Landau-Ginzburg theory. This work demonstrates that a MOSFET with a ferroelectric layer integrated in the gate stack could have nondegraded or even improved subthreshold swing and transconductance at high temperature even though the hysteresis window is reduced. As a consequence, we suggest that for ferroelectric transistors with appropriately designed Curie temperatures, the performance degradation of logic or analog circuits, nowadays operating near 100 degrees C, could be avoided. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3467471]

American Institute of Physics2010

Leakage mechanisms and contact technologies in InAlN/GaN high electron mobility transistors

Lorenzo Lugani

GaN based electronic devices have progressed rapidly over the past decades and are nowadays starting to replace Si and classical III-V semiconductors in power electronics systems and high power RF amplifiers. AlGaN/GaN heterostructures have been, until recently, the materials system of choice for nitride based electronics. The limits of AlGaN/GaN technologies are now known and alternative routes able to overcome them are actively investigated. Nearly lattice-matched InAlN/GaN heterostructures have emerged as viable solutions for extending the frequency range achievable by GaN based devices. These heterostructures have also proven a very high thermal stability, becoming of high interest for extreme environment applications. However, despite those great potentials, InAlN/GaN based devices, in particular high electron mobility transistors, have suffered from high leakage currents, strong short channel effects and low breakdown voltage that made them not competitive with respect to AlGaN/GaN technologies. The goal of this thesis is to investigate, understand and control the mechanisms that limit the performance of InAlN/GaN based transistors. Particular attention in this thesis will be given to leakage currents, having gate or buffer origin. Concerning gate leakage currents, an accurate model for InAlN/GaN heterostructures will be established and the expected presence of deep levels will be confirmed by means of photocapacitance spectroscopy. Based on these results, it will be shown that two conduction mechanisms contribute to gate leakage currents. A first mechanism dominates in heterostructures with thin (

EPFL2015

LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

Taifang Wang

GaN metal-oxide-semiconductor high electron mobility transistors (MOS)HEMTs) offer outstanding properties for next-generation power electronics devices. The high conductivity, high voltage blocking capability, high operation frequency, and device-level integration can be achieved on the same tech-nology platform. Moreover, the development of large-scale GaN-on-Si substrate reduces the cost of GaN lateral devices. That GaN power device has already been widely used in today's consumer electronics, and communications base stations with its superiority of power density, and energy efficiency.Despite the ideal side of GaN material for power transistor, the junction less structure of HEMT made it hard to achieve enhancement-mode (e-mode) operation. Existing solutions either rely on complicated processes or sacrifice device performance. A simple process, high performance, and reliable operation e-mode device are desired. This thesis proposes Li doped NiO as gate material combined with Tri-gate structure to achieve e-mode operation. This relied on a simple oxide deposition process, without using barrier recess or re-growth, and achieved a high-quality interface. These critical characteristics haven't been demonstrated on gate stack engineering for normally-off devices and reveal the outstanding stability of LiNiO as a junction gate.Moreover, to maximize the GaN power transistor performance boundary, a multi-channel junction gate device was developed, which uses multiple 2DEG channels to significantly reduce the device resistance while still operating at high breakdown voltage (VBR). The multi-channel junction gate de-vice presents state-of-the-art performance, stable operation, and simple process e-mode GaN transistor. Apart from achieving e-mode operation, the possibility of device-level integration was also explored. Reverse current conduction ability was achieved together with good on-state performance and voltage blocking capability. And the alternative method of regulating electric field to Tri-gate by grayscale lithography was developed. The results in this thesis reveal the great value of using oxide semiconductor LiNiO as junction gate, demonstrating high performance, e-mode, and reliable device, and unleashing the performance potential through multi-channel epitaxy.

EPFL2022

LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

Taifang Wang

EPFL2022