Publication

Opportunities and challenges of 2D materials in back-end-of-line interconnect scaling

Publications associées (32)

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Kilowatt-range Picosecond Switching Based on Microplasma Devices

Elison de Nazareth Matioli, Remco Franciscus Peter van Erp, Armin Jafari

Plasma formation in micro- and nano-scales enables an ultrahigh-dv/dt picosecond switching in an integrated circuit form factor. Such on-chip plasma devices could provide a transformative approach to achieving high-power levels at very high frequencies, fa ...

2021

Reconfigurable electronics based on metal-insulator transition

Wolfgang Amadeus Vitale

The vast majority of disruptive innovations in science and technology has been originated from the discovery of a new material or the way its properties have been exploited to create novel devices and systems. New advanced nanomaterials will have a lasting ...

EPFL2016

This thesis presents a collection of experimental results about the large-area growth of single-layer graphene and MoS2 films. In addition, we present the results of electrical characterisation of two-dimensional (2D) materials in direct current (DC) and r ...

EPFL2016

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The development of interconnections suitable for radio- frequency (RF) and millimeter-wave (mm-wave) applications is of foremost importance for the feasibility of high-quality substrate-integrated devices. For this purpose, we introduce and validate the te ...

2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Nico de Rooij, Danick Briand, Andres Felipe Vasquez Quintero

In this paper, a low temperature flip-chip integration technique for Si bare dies is demonstrated on flexible PET substrates with screen-printed circuits. The proposed technique is based on patterned blind vias in dry film photoresist (DP) filled with isot ...

Iop Publishing Ltd2015

In the framework of the NanoTera project CabTuRes, a system-in-package for a nano-resonator was proposed, integrating CMOS driving electronics and vacuum encapsulation. This doctoral research aimed to investigate 3D-integration technologies for a Single-Wa ...

EPFL2013

An implantable biosensor array for personalized therapy applications

Andrea Cavallini

At present, most of the tests involved in personalized medicine are complex and must be conducted in specialized centers. The development of appropriate, fast and inexpensive diagnostic technologies can encourage medical personnel in performing preventive ...

EPFL2013

Design iterations on Lego R - like MEMS bricks

Titus Cieslewski

This semester project is a proof of concept for the production of Lego R -like bricks in MEMS. Several design iterations have been made using milimeter-scale, o-chip fabrication methods. The nal product consists of 3mmx6mmx2mm bricks made of PDMS enriched ...

2013

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

John Richard Thome, Michail Zervas, Yusuf Leblebici, Yassir Madhour, Bruno Michel

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconn ...

IEEE2013