An Analog-Assisted Digital LDO With Single Subthreshold Output pMOS Achieving 1.44-fs FOM

This letter describes an analog-assisted digital LDO that cascades a conventional digital LDO structure with a single, large output pMOS biased in subthreshold to enable fast response to output voltage droop. By digitally controlling the gate voltage of the output pMOS, the operating regime of the output transistor is decoupled from the input voltage. In addition, a 2-pF capacitor between the output voltage and the gate of the output pMOS creates a high-pass path to boost the output current when voltage droops occur. The proposed design is fabricated in 28-nm CMOS, and it enables a uniform transient response over an input voltage range of 0.5-0.9 V. The measured voltage droop when load current changes from 10 to 60 mA (1-ns edge time) is 110 mV at input voltages of both 0.5 and 0.9 V, resulting in a speed FOM of 1.44 fs.