Publication
Method for reading and writing unreliable memories and a corresponding memory controller device and memory
Publications associées (92)
Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities
Even if Dennard scaling came to an end fifteen years ago, Moore's law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...
EPFL2021Preventing Use-After-Free Attacks with Fast Forward Allocation
Memory-unsafe languages are widely used to implement critical systems like kernels and browsers, leading to thousands of memory safety issues every year. A use-after-free bug is a temporal memory error where the program accidentally visits a freed memory l ...
USENIX ASSOC2021SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators
Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee
Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...
2020Access pattern based optimization of memory access
Anastasia Ailamaki, Georgios Psaropoulos
A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...
2020Gain-Cell Embedded DRAMs: Modeling and Design Space
Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti
Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020Distributed Computing with Modern Shared Memory
In this thesis, we revisit classic problems in shared-memory distributed computing through the lenses of (1) emerging hardware technologies and (2) changing requirements. Our contributions consist, on the one hand, in providing a better understanding of th ...
EPFL2020Gain-Cell Embedded DRAMs: Modeling and Design Space
Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti
Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...
IEEE2020Prefetched Address Translation
Edouard Bugnion, Boris Robert Grot, Dmitrii Ustiugov
With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a ...
ASSOC COMPUTING MACHINERY2019A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories
David Atienza Alonso, Marina Zapater Sancho, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Yasir Mahmood Qureshi, Edouard Giacomin, João Miguel Morgado Pereira Vieira
The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. ...
2019In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA
Paolo Ienne, Mikhail Asiatici, Gabor Andras Csordas
For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers ...
IEEE COMPUTER SOC2019