LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

GaN metal-oxide-semiconductor high electron mobility transistors (MOS)HEMTs) offer outstanding properties for next-generation power electronics devices. The high conductivity, high voltage blocking capability, high operation frequency, and device-level integration can be achieved on the same tech-nology platform. Moreover, the development of large-scale GaN-on-Si substrate reduces the cost of GaN lateral devices. That GaN power device has already been widely used in today's consumer electronics, and communications base stations with its superiority of power density, and energy efficiency.Despite the ideal side of GaN material for power transistor, the junction less structure of HEMT made it hard to achieve enhancement-mode (e-mode) operation. Existing solutions either rely on complicated processes or sacrifice device performance. A simple process, high performance, and reliable operation e-mode device are desired. This thesis proposes Li doped NiO as gate material combined with Tri-gate structure to achieve e-mode operation. This relied on a simple oxide deposition process, without using barrier recess or re-growth, and achieved a high-quality interface. These critical characteristics haven't been demonstrated on gate stack engineering for normally-off devices and reveal the outstanding stability of LiNiO as a junction gate.Moreover, to maximize the GaN power transistor performance boundary, a multi-channel junction gate device was developed, which uses multiple 2DEG channels to significantly reduce the device resistance while still operating at high breakdown voltage (VBR). The multi-channel junction gate de-vice presents state-of-the-art performance, stable operation, and simple process e-mode GaN transistor. Apart from achieving e-mode operation, the possibility of device-level integration was also explored. Reverse current conduction ability was achieved together with good on-state performance and voltage blocking capability. And the alternative method of regulating electric field to Tri-gate by grayscale lithography was developed. The results in this thesis reveal the great value of using oxide semiconductor LiNiO as junction gate, demonstrating high performance, e-mode, and reliable device, and unleashing the performance potential through multi-channel epitaxy.

Contact Effects in Organic Transistors

Frederik Sebastian Ante

Organic thin-film transistors (TFTs) are of interest for applications that require electronic functionality with low or medium complexity distributed over large areas on unconventional substrates, such as flexible polymeric films. Generally these are applications in which the use of silicon devices and circuits is technically or economically not feasible. Examples include flexible displays and large-area sensor arrays. The static and dynamic performance of state-of-the-art organic p-channel transistors is already sufficient for applications in which the transistors operate with frequencies of a few tens of kilohertz. Strategies to improve the performance of organic TFTs include improvements in the field-effect mobility of the charge carriers in the organic semiconductor layer and more aggressive scaling of the transistor dimensions. Additional advances are also required in the environmental and operational stability of organic TFTs and in the application of controlled contact doping for the reduction of the contact resistance of organic TFTs. In this thesis, high-resolution silicon stencil masks are introduced to pattern top-contact organic TFTs with lateral dimensions as small as 0.8 µm. Taking advantage of the recently synthesized high-mobility air-stable organic semiconductor dinaphtho[2,3-b:2'3'-f]thieno[3,2-b]thiophene (DNTT), polycrystalline organic p-channel TFTs with excellent air-stability and an intrinsic mobility of 3.4 cm2/Vs were fabricated. The transistors employ an ultra-thin gate dielectric based on a plasma-grown oxide layer in combination with an organic self-assembled monolayer (gate capacitance ∼1 µF/cm2), allowing the TFTs to operate with low voltages of about 3 V. Transistors with dimensions of less than 100 nm were manufactured using polymer resist shadow masks that have been fabricated by electron-beam lithography. Thanks to the 5 nm thick gate dielectric the TFTs show no short-channel effects. The subthreshold swing, the on/off current ratio, and the threshold voltage are comparable to long-channel TFTs with lateral dimensions of ∼100 µm. However, organic transistors with reduced dimensions are often limited by the energy barrier at the interface between the semiconductor and the source/drain contacts. One approach to reduce this energy barrier is the introduction of a strong electron acceptor into the contact area that acts as a dopant. With contact doping, the contact resistance is reduced and the effective mobility of short-channel TFTs increases by more than 200%. Transistors (without doping) with lateral dimensions of ∼1 µm have a transconductance of about 1 S/m, so that the TFTs operate at frequencies of several megahertz. The influence of strongly reduced lateral dimensions on the contact resistance and the maximum operation frequency is investigated and scaling limitations are discussed.

EPFL2011

Modélisation physique d'un transistor de puissance IGBT

Serge Pittet

The IGBT transistor, associating the conduction advantages of the bipolar transistor and the switching advantages of the MOSFET transistor, is widely used in medium and high power applications with an operating voltage of 1.2kV to 4.5kV. New topologies, reducing the losses in the semi-conductor devices, are often proposed and have to be validated through a simulation tool. The finite element method (FEM) simulators accurately analyse losses in components, but the associated simulation time is so long that they cannot be used for complex topologies in power electronics. An equivalent transistor macromodel, correctly and quickly predicting currents and voltages on the element is needed. This thesis proposes an IGBT transistor model based on semiconductor physics and validated through a comparison with finite element simulator results. The model yields very good results regardless of transistor load and operating point. Base conduction is modelled using a novel equivalent charge approach. This results in a relatively simple macromodel with a good representation of the static and dynamic phenomena. The solving method of the Poisson equation has been revisited to fit recent changes of the internal structure of IGBT transistors. All approximations have been validated through fi- nite element analysis using an appropriate simulation set. The approximation of the internal MOSFET, even though based on existing models, takes into account the specificities of the IGBT transistor structure. It shows the degenerated properties of the internal MOSFET compared to the properties of a standard MOSFET, regardless of the operating point. Using intermediate potentials within the semiconductor structure allows a separate analysis of the different voltage contributions. A complete IGBT transistor macromodel has been developed and tested in different power electronics structures. Good results were obtained in all the tested structures with the proposed IGBT transistor macromodel. Parameter extraction can easily be automated using a mathematical tool such as Matlab and only requires few measurements on the device. The obtained results can then be quickly adapted to an other IGBT device.

EPFL2005

Ferroelectric gate on AlGaN/GaN heterostructures

Lisa Malin

The capability of switching the spontaneous polarisation under an applied electric field in ferroelectric materials can be exploited for the use in low power, non-volatile, re-writable memory devices. Currently available commercially is ferroelectric random access memory, FeRAM, which allows for high speed, low voltage and greater write-erase endurance compared to its two main competitors, Flash and EEPROM, when using the one transistor – one capacitor configuration. However, it is desired to further optimise the configuration in order to obtain better densification, faster access time and better reliability. One way to do such is to pass from the ferroelectric capacitors and develop ferroelectric field effect transistors. Exploiting the phenomenon of ferroelectricity and integrating ferroelectrics with the semiconductor technology has not been simple. The FeFET has been demonstrated using a silicon-based transistor, however commercial devices are not available. Challenges arise mainly due to the high temperature deposition of perovskite ferroelectrics causing the degradation of the ferroelectric/semiconductor interface due to inter-diffusion. Acquiring long term retention of the transistor behavior has also been problematic due to phenomenons such as charge injection and depolarisation. In this thesis a new approach to the problem of semiconductor devices with a ferroelectric gate is explored. Instead of using a silicon-based device, semiconductor heterostructures are investigated. Combining the high mobility channel existing in semiconductor heterostructures, with the non-volatile switching of the polarisation in the ferroelectric gate can pave the way to novel future devices. The AlGaN/GaN semiconductor heterostructure was chosen for two main reasons. The first is a two dimensional electron gas, 2DEG, located at the AlGaN/GaN interface which possesses better transport properties than a single layered semiconductor. Secondly, GaN and its alloys are known to have large chemical and temperature stability making them ideal to withstand the high temperature deposition process of perovskite ferroelectrics. The deposition of two ferroelectric layers onto the AlGaN heterostructure were investigated. Lead zirconium titanate, PZT, a traditional perovskite ferroelectric deposited at high temperature, was chosen for its high remanent polarisation and low coercive field. An alternative ferroelectric gate, the co-polymer poly(vinylidene fluoride/trifluoroethylene), P(VDF/TrFE)(70:30) was deposited and of interest due its low crystallisation temperature and low dielectric constant. Its remanent polarisation is smaller and coercive field larger than that of PZT, but were determined sufficient to observe the depletion effect in the two dimensional electron gas. The goals accomplished in this research were: Development of Ferroelectric Gate Processing: Deposition processes of the ferroelectric layers were developed and optimised in order to obtain a high quality ferroelectric, while maintaining the original transport properties of AlGaNs 2DEG. The processing of HfO2 and MgO buffer layers were developed and investigated for their effects on limiting unwanted inter-diffusion and charge injection. PZT Gate on Al0.3Ga0.7N: The first successful development and observation of a PZT gate on a Al0.3Ga0.7N/GaN heterostrucutre was accomplished. A (111) oriented PZT(40:60) ferroelectric gate on the Al0.3Ga0.7N heterostructure depleted the sheet resistance of the 2DEG by a factor of three when poling the PZT layer with –40V directly to the conductive cantilever used in a piezoresponse force microscope. This decrease in sheet resistance was stable for more than three days. P(VDF/TrFE)(70:30) Gate on Al0.3Ga0.7N: The ferroelectric co-polymer P(VDF/TrFE) (70:30) was investigated as a gate on the Al0.3Ga0.7N heterostructure. When the P(VDF/TrFE) was poled with –30V to a top electrode the sheet resistance was modulated by a factor three, however there was no retention of this modulation. Ferroelectric Spontaneous Polarisation on a Semiconductor Heterostructure: It was theoretically derived that when depositing a ferroelectric layer onto a semiconductor heterostructure its spontaneous polarisation is dramatically reduced due to the depolarisation field and may be suppressed completely. This decay in spontaneous polarisation can be minimised by using a ferroelectric layer with a small dielectric constant, which justifies the use of ferroelectric polymers as the gate material. Domain Writing:The technique of domain writing using piezoresponse force microscopy showed that it was possible to create domain patterning on the ferroelectric layers that were deposited onto the Al0.3Ga0.7N heterostructure with sub-micron line resolution, on the order of 300nm or better. Using ferroelectrics on semiconductors is not only limited to ferroelectric memory devices. Other applications could be ferroelectric nano-lithography, where a ferroelectric pattern is written with a piezoresponse force microscope, PFM, and this pattern is projected onto the transistors channel, potentially creating quantum/ballistic devices. The challenge of integrating ferroelectrics with semiconductors has yet to be fully understood. One of the main advancements that was reached with this research is the understanding of the decrease of the spontaneous polarisation when a ferrroelectric layer is deposited onto a semiconductor heterostructure of finite thickness. The maximisation of the ferroelectrics polarisation on 20nm of Al0.3Ga0.7N can be obtained when minimising the dielectric constant of the ferroelectric layer. The current challenge is to get a better physical understanding of the limitation of the retention of the spontaneous polarisation, while discovering methods for its improvement.

EPFL2007